From: Gregory CLEMENT <gregory.clement@bootlin.com>
To: Baruch Siach <baruch@tkos.co.il>
Cc: Andrew Lunn <andrew@lunn.ch>,
Florian Fainelli <f.fainelli@gmail.com>,
Jason Cooper <jason@lakedaemon.net>,
netdev@vger.kernel.org, Linus Walleij <linus.walleij@linaro.org>,
Russell King <linux@armlinux.org.uk>,
Ori Shemtov <ori.shemtov@solid-run.com>,
linux-arm-kernel@lists.infradead.org,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Subject: Re: [PATCH 2/2] arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal
Date: Fri, 30 Nov 2018 18:45:35 +0100 [thread overview]
Message-ID: <87ftvimpc0.fsf@bootlin.com> (raw)
In-Reply-To: <d7d0516199244af29efdd5231313a6519f5a4350.1539687053.git.baruch@tkos.co.il> (Baruch Siach's message of "Tue, 16 Oct 2018 13:50:53 +0300")
Hi Baruch,
On mar., oct. 16 2018, Baruch Siach <baruch@tkos.co.il> wrote:
> This reset signal controls the Marvell 1512 1G PHY.
>
> Note that current implementation queries the PHY over the MDIO bus
> (get_phy_device() call from of_mdiobus_register_phy()) before reset
> signal deassert. If the PHY reset signal is asserted at boot time, PHY
> registration fails. So current code relies on the bootloader to deassert
> the reset signal.
Applied on mvebu/dt64
Thanks,
Gregory
>
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> ---
> arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> index af1310c53bc8..73df0ef5e0c4 100644
> --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> @@ -337,6 +337,10 @@
> */
> marvell,reg-init = <3 16 0 0x1017>;
> reg = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&cp0_copper_eth_phy_reset>;
> + reset-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <10000>;
> };
>
> switch0: switch0@4 {
> --
> 2.19.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Gregory CLEMENT <gregory.clement@bootlin.com>
To: Baruch Siach <baruch@tkos.co.il>
Cc: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
linux-arm-kernel@lists.infradead.org,
Russell King <linux@armlinux.org.uk>,
Ori Shemtov <ori.shemtov@solid-run.com>,
Florian Fainelli <f.fainelli@gmail.com>,
netdev@vger.kernel.org, Linus Walleij <linus.walleij@linaro.org>
Subject: Re: [PATCH 2/2] arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal
Date: Fri, 30 Nov 2018 18:45:35 +0100 [thread overview]
Message-ID: <87ftvimpc0.fsf@bootlin.com> (raw)
In-Reply-To: <d7d0516199244af29efdd5231313a6519f5a4350.1539687053.git.baruch@tkos.co.il> (Baruch Siach's message of "Tue, 16 Oct 2018 13:50:53 +0300")
Hi Baruch,
On mar., oct. 16 2018, Baruch Siach <baruch@tkos.co.il> wrote:
> This reset signal controls the Marvell 1512 1G PHY.
>
> Note that current implementation queries the PHY over the MDIO bus
> (get_phy_device() call from of_mdiobus_register_phy()) before reset
> signal deassert. If the PHY reset signal is asserted at boot time, PHY
> registration fails. So current code relies on the bootloader to deassert
> the reset signal.
Applied on mvebu/dt64
Thanks,
Gregory
>
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> ---
> arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> index af1310c53bc8..73df0ef5e0c4 100644
> --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
> @@ -337,6 +337,10 @@
> */
> marvell,reg-init = <3 16 0 0x1017>;
> reg = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&cp0_copper_eth_phy_reset>;
> + reset-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <10000>;
> };
>
> switch0: switch0@4 {
> --
> 2.19.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
next prev parent reply other threads:[~2018-11-30 17:45 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-16 10:50 [PATCH 1/2] arm64: dts: clearfog-gt-8k: fix USB regulator gpio polarity Baruch Siach
2018-10-16 10:50 ` Baruch Siach
2018-10-16 10:50 ` [PATCH 2/2] arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal Baruch Siach
2018-10-16 10:50 ` Baruch Siach
2018-11-30 17:45 ` Gregory CLEMENT [this message]
2018-11-30 17:45 ` Gregory CLEMENT
2018-11-30 17:45 ` [PATCH 1/2] arm64: dts: clearfog-gt-8k: fix USB regulator gpio polarity Gregory CLEMENT
2018-11-30 17:45 ` Gregory CLEMENT
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