Re: [PATCH] drm/i915/execlists: Include reset depth in traces

[Mika Kuoppala <mika.kuoppala@linux.intel.com>]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Show the reset depth (the tasklet disable count) in the GEM_TRACE to
> indicate when we might not expect tasklets to be flushed.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 178a74e29400..257d6f5f44d1 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1834,7 +1834,8 @@ execlists_reset_prepare(struct intel_engine_cs *engine)
>  	struct i915_request *request, *active;
>  	unsigned long flags;
>  
> -	GEM_TRACE("%s\n", engine->name);
> +	GEM_TRACE("%s: depth<-%d\n", engine->name,
> +		  atomic_read(&execlists->tasklet.count));

Interesting notation but yes, entry and exit will be visible.

I can't think of the details on a case when this would matter.
Regardless, the knowledge of at what point we flushed or not
is beneficial.

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

>  
>  	/*
>  	 * Prevent request submission to the hardware until we have
> @@ -1982,7 +1983,8 @@ static void execlists_reset_finish(struct intel_engine_cs *engine)
>  	 */
>  	__tasklet_enable_sync_once(&execlists->tasklet);
>  
> -	GEM_TRACE("%s\n", engine->name);
> +	GEM_TRACE("%s: depth->%d\n", engine->name,
> +		  atomic_read(&execlists->tasklet.count));
>  }
>  
>  static int intel_logical_ring_emit_pdps(struct i915_request *rq)
> -- 
> 2.18.0
>
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