From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Zhang, Xiong Y" <xiong.y.zhang@intel.com>,
"ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/i915: Setting pch_id for Gen7.5+ in virtual environment
Date: Thu, 30 Mar 2017 09:33:42 +0300 [thread overview]
Message-ID: <87fuhv46k9.fsf@intel.com> (raw)
In-Reply-To: <8082FF9BCB2B054996454E47167FF4EC1C491B42@SHSMSX104.ccr.corp.intel.com>
On Thu, 30 Mar 2017, "Zhang, Xiong Y" <xiong.y.zhang@intel.com> wrote:
>> On Wed, Mar 29, 2017 at 05:02:47PM +0800, Xiong Zhang wrote:
>> I'm not 100% sure the ULT/ULX <=> LP thing always holds. I *think* it
>> should but I've never been able to convince myself totally.
> [Zhang, Xiong Y] For BDW ULT/ULX, it should be LP. A picture from https://gfxspecs.intel.com/Predator/Home/Index/4216 could confirm this.
While that picture confirms ULT/ULX uses LP PCH, it also confirms
there's a non-ULT/ULX BDW with LP PCH, and on that the patch chooses the
wrong PCH type.
> For HSW ULT/ULX, I couldn't find a material to confirm this.
> Anyway I copy this condition from the WARN_ON() in intel_detect_pch()
The conditions in intel_detect_pch() are quite different, as it has
actually detected the PCH, and the warnings are just about unexpected
(and potentially unsupported) pairs of physical hardware.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
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next prev parent reply other threads:[~2017-03-30 6:33 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-29 9:02 [PATCH] drm/i915: Setting pch_id for Gen7.5+ in virtual environment Xiong Zhang
2017-03-29 9:15 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-03-29 11:22 ` [PATCH] " Ville Syrjälä
2017-03-30 5:39 ` Zhang, Xiong Y
2017-03-30 6:33 ` Jani Nikula [this message]
2017-03-31 9:37 ` Martin Peres
2017-04-12 14:00 ` Martin Peres
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