Re: [PATCH] drm/i915: Include power-management state in gpu error dump

[Mika Kuoppala <mika.kuoppala@linux.intel.com>]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> On Thu, Mar 02, 2017 at 05:29:18PM +0200, Mika Kuoppala wrote:
>> Chris Wilson <chris@chris-wilson.co.uk> writes:
>> 
>> > Useful for double checking that the device is powered up when it hung,
>> > include both the status of the power management and our rpm wakelock.
>> >
>> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/i915_drv.h       | 2 ++
>> >  drivers/gpu/drm/i915/i915_gpu_error.c | 4 ++++
>> >  2 files changed, 6 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> > index 66f19924828a..28d8e95b4a14 100644
>> > --- a/drivers/gpu/drm/i915/i915_drv.h
>> > +++ b/drivers/gpu/drm/i915/i915_drv.h
>> > @@ -937,6 +937,8 @@ struct i915_gpu_state {
>> >  	char error_msg[128];
>> >  	bool simulated;
>> >  	bool awake;
>> > +	bool wakelock;
>> > +	bool suspended;
>> >  	int iommu;
>> >  	u32 reset_count;
>> >  	u32 suspend_count;
>> > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
>> > index b4ae1464e0ab..8e14986f123c 100644
>> > --- a/drivers/gpu/drm/i915/i915_gpu_error.c
>> > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>> > @@ -633,6 +633,8 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
>> >  	}
>> >  
>> >  	err_printf(m, "GT awake: %s\n", yesno(error->awake));
>> > +	err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
>> 
>> Why not print the count as we have it?
>
> I didn't consider it worthwhile knowing the count without the who. For
> the purpose of debugging a hang, I just had one question: was the device
> powered, did we think it should be?

1 vs >100 could be revealing, but perhaps theoretical.
I can live with this.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> -Chris
>
> -- 
> Chris Wilson, Intel Open Source Technology Centre
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