From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mika Kuoppala Subject: Re: [PATCH] drm/i915: setup workarounds on reset Date: Wed, 20 Nov 2013 13:47:46 +0200 Message-ID: <87fvqrnvkt.fsf@gaia.fi.intel.com> References: <1384785284-1435-1-git-send-email-mika.kuoppala@intel.com> <20131118162401.GD8203@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 4F885105978 for ; Wed, 20 Nov 2013 03:48:07 -0800 (PST) In-Reply-To: <20131118162401.GD8203@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Daniel Vetter writes: Hi Daniel, > On Mon, Nov 18, 2013 at 04:34:44PM +0200, Mika Kuoppala wrote: >> Large parts of hw initialization is behind per gen >> clock gating functions. Including workarounds. >> >> Call intel_modeset_init_hw after reset so that we >> set these up correctly. >> >> Signed-off-by: Mika Kuoppala >> --- >> drivers/gpu/drm/i915/i915_drv.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c >> index c2e00ed..2908f7f 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.c >> +++ b/drivers/gpu/drm/i915/i915_drv.c >> @@ -798,6 +798,8 @@ int i915_reset(struct drm_device *dev) >> drm_irq_uninstall(dev); >> drm_irq_install(dev); >> intel_hpd_init(dev); >> + >> + intel_modeset_init_hw(dev); > > Currently the idea is that w/as which get nuked by the gt reset should be > put into the respective ring_init function in intel_ringbuffer.c. This > disdinction is important since init_clock_gating gets called fairly early > in the resume/load sequence before most of the gem stuff is set up. And > the w/a in the ring_init functions are carefully ordered wrt the ring (re) > enabling. > > So which bit/register is the culprit here? Here is output from the test on ivb, after drv_hangman: FAIL WaDisableEarlyCull:ivb OK WaDisableBackToBackFlipFix:ivb FAIL WaDisablePSDDualDispatchEnable:ivb FAIL WaDisableRHWOptimizationForRenderHang:ivb FAIL WaApplyL3ControlAndL3ChickenMode:ivb OK WaForceL3Serialization:ivb OK WaDisableRCZUnitClockGating:ivb OK WaCatErrorRejectionIssue:ivb FAIL WaVSRefCountFullforceMissDisable:ivb FAIL WaDisable4x2SubspanOptimization:ivb 10 workarounds tested, 4 passed, 6 failed Test assertion failure function main, file drv_workarounds.c:119: Failed assertion: check_workarounds(&ivb_workarounds[0], "ivb") == 0 Test can be found in here: https://github.com/mkuoppal/intel-gpu-tools/tree/was -Mika