From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:33786) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RzFt0-0005A8-EF for qemu-devel@nongnu.org; Sun, 19 Feb 2012 18:09:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RzFsz-0003lB-AS for qemu-devel@nongnu.org; Sun, 19 Feb 2012 18:09:42 -0500 Received: from ozlabs.org ([203.10.76.45]:37371) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RzFsz-0003ks-0V for qemu-devel@nongnu.org; Sun, 19 Feb 2012 18:09:41 -0500 From: Rusty Russell In-Reply-To: <87vcnyc7cg.fsf@rustcorp.com.au> References: <1326487969-12462-1-git-send-email-peter.maydell@linaro.org> <1326487969-12462-3-git-send-email-peter.maydell@linaro.org> <87fwf5ebjw.fsf@rustcorp.com.au> <87vcnyc7cg.fsf@rustcorp.com.au> Date: Mon, 20 Feb 2012 09:37:07 +1030 Message-ID: <87fwe68lt0.fsf@rustcorp.com.au> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Subject: [Qemu-devel] [PATCH] arm: make sure that number of irqs can be represented in GICD_TYPER. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org, android-virt@lists.cs.columbia.edu, patches@linaro.org We currently assume that the number of interrupts (ITLinesNumber in the architecture reference manual) is divisible by 32, since we present it to the guest when it reads GICD_TYPER (in gic_dist_readb()) as (N - 32) / 1. Signed-off-by: Rusty Russell diff --git a/hw/arm_gic.c b/hw/arm_gic.c index fa6a60a..6446800 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -818,6 +818,15 @@ static void gic_init(gic_state *s, int num_irq) hw_error("requested %u interrupt lines exceeds GIC maximum %d\n", num_irq, GIC_MAXIRQ); } + /* ITLinesNumber is represented as (N - 32) / 1 (see + * gic_dist_readb) so this is an implementation imposed + * restriction, not an architectural one: + */ + if (s->num_irq < 32 || (s->num_irq % 32)) { + hw_error("%d interrupt lines unsupported: not divisible by 32\n", + num_irq); + } + qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, s->num_irq - GIC_INTERNAL); for (i = 0; i < NUM_CPU(s); i++) { sysbus_init_irq(&s->busdev, &s->parent_irq[i]);