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From: Kevin Hilman <khilman@deeprootsystems.com>
To: "Nayak, Rajendra" <rnayak@ti.com>
Cc: "Högander Jouni" <jouni.hogander@nokia.com>,
	"linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>,
	"Derrick, David" <dderrick@ti.com>,
	"Woodruff, Richard" <r-woodruff2@ti.com>
Subject: Re: [PATCH 02/04] OMAP3: PM: Prevent AUTO_RET and AUTO_OFF being enabled simultaneously
Date: Mon, 29 Jun 2009 14:45:47 -0700	[thread overview]
Message-ID: <87fxdi7lys.fsf@deeprootsystems.com> (raw)
In-Reply-To: <5A47E75E594F054BAF48C5E4FC4B92AB0305A53FD3@dbde02.ent.ti.com> (Rajendra Nayak's message of "Wed\, 17 Jun 2009 11\:57\:40 +0530")

"Nayak, Rajendra" <rnayak@ti.com> writes:

>>"Nayak, Rajendra" <rnayak@ti.com> writes:
>>
>>>From: Högander Jouni [mailto:jouni.hogander@nokia.com] 
>>>>
>>>>ext Rajendra Nayak <rnayak@ti.com> writes:
>>>>
>>>>> There is a design requirement in OMAP3 that Auto_RET and AUTO_OFF
>>>>> should not be set together. The PRCM FSM  has been coded assuming
>>>>> that SW will set either auto_ret or auto_off bit depending on
>>>>> whether the core has been programmed to go into open switched
>>>>> logic retention state or OFF state. They are mutually exclusive.
>>>>
>>>>So we don't have to do this if closed switch retention is used? (This
>>>>is what is currently used in linux-omap:pm)
>>>
>>> Currently in the pm branch AUTO_RET is enabled at init and kept
>>> enabled. While attempting a OFF state AUTO_OFF is enabled also
>>> leaving AUTO_RET and AUTO_OFF both enabled.
>>
>>A little more clarification needed, in particular whether or how
>>this affects closed-switch retention.
>
> Sorry, that was a wrong description. AUTO_RET could be used to scale the voltage
> down even in case of CSWR and not just OSWR.
>
> The idea of this patch was to enable auto voltage scaling only for the last 3 C states.
>
>  *	C5 . MPU CSWR + Core CSWR - AUTO RET enabled
>  *	C6 . MPU OFF + Core CSWR - AUTO RET enabled
>  *	C7 . MPU OFF + Core OFF - AUTO OFF enabled.
>
> For the rest of the Lower C states the decision of not enabling AUTO
> RET/OFF was to keep the latency for such states down.
>
> Especially with SR enabled having AUTO RET/OFF enabled for say a MPU
> RET/CORE inactive state would mean a 2 level voltage change. First
> to scale from SR autocompensated level to the actual OPP voltage
> level (That's done when you disable SR) and then from the there to
> the AUTO RET level.  So say you hit MPU RET/CORE inactive state at
> OPP3 (1.2v) which has a SR autocompensated voltage to 1.08v, then
> you would scale from 1.08->1.2->0.975.  That might be too much of
> additional latency to incure in case of a MPU RET/CORE inactive
> state.
>

OK, I've updated the patch description on this one and will push to PM
branch (and pm-2.6.29)

Kevin
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  reply	other threads:[~2009-06-29 21:45 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-06-16 11:52 [PATCH 01/04] OMAP3: PM: Disable PER DPLL idle before OFF, reduces OFF latency by 20ms Rajendra Nayak
2009-06-16 11:52 ` [PATCH 02/04] OMAP3: PM: Prevent AUTO_RET and AUTO_OFF being enabled simultaneously Rajendra Nayak
2009-06-16 11:52   ` [PATCH 03/04] OMAP3: PM: Fix I2C voltage levels send to T2 for different Power modes Rajendra Nayak
2009-06-16 11:52     ` [PATCH 04/04] OMAP3: PM: Update sleep/wakeup sequence and device grp associations Rajendra Nayak
2009-06-29 22:29       ` Kevin Hilman
2009-06-29 21:48     ` [PATCH 03/04] OMAP3: PM: Fix I2C voltage levels send to T2 for different Power modes Kevin Hilman
2009-06-16 12:39   ` [PATCH 02/04] OMAP3: PM: Prevent AUTO_RET and AUTO_OFF being enabled simultaneously Högander Jouni
2009-06-16 13:16     ` Nayak, Rajendra
2009-06-16 14:28       ` Kevin Hilman
     [not found]         ` <92CDD168D1E81F4F9D3839DC45903FC6536982E1@dlee03.ent.ti.com>
2009-06-16 17:28           ` Kevin Hilman
2009-06-17 16:52             ` Derrick, David
2009-06-17  6:27         ` Nayak, Rajendra
2009-06-29 21:45           ` Kevin Hilman [this message]
2009-06-16 12:52 ` [PATCH 01/04] OMAP3: PM: Disable PER DPLL idle before OFF, reduces OFF latency by 20ms Högander Jouni
2009-06-16 13:17   ` Nayak, Rajendra
2009-06-16 14:21 ` Kevin Hilman
2009-06-16 16:09   ` Derrick, David
2009-06-17  8:33     ` Paul Walmsley

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