From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 29CA6C53200 for ; Wed, 29 Jul 2026 23:09:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A7F0410E0AB; Wed, 29 Jul 2026 23:09:38 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="F8UQr3eg"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id C8FA110E0AB for ; Wed, 29 Jul 2026 23:09:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1785366578; x=1816902578; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=BCSW1eV2Tc0v9TzKWLH/ffV0sRDXguaFQ4OkYUFqnVw=; b=F8UQr3egzkbJj5MDhRhQRJCQfh281kdR4YMEzPM33dXk5+819rLmMMDt wSUGVGBpF/XBUBSuyMo9ILKLsqnYHWym9a0OF0Uih/S+bbYOALRtdtKAw 5WlwANRkZqGS5g7XvBO8vrrwkhNOKEBwbKcQoC45vecmzfW9D4j373GKw Ej154nqkUS21l+LOfGq3SHebgjlfrEcT1sI90W6QKAIuP+UWIP8id79fB WFPT3ZwCGLrM0uNwtHvzoPGH1L9EhZ9XHw8Dh1CGYBghvhV7G297XfLgL 4B/nQFvEDZJDGbXskCYWDAxMAbDMhr9Vb1ile2aYKj2jIq8hP2nIPgJst A==; X-CSE-ConnectionGUID: Xi/41D2WTxy5czvyjQrKBQ== X-CSE-MsgGUID: YpAJJ22sRp2eDTJfTZfH5Q== X-IronPort-AV: E=McAfee;i="6800,10657,11859"; a="85999679" X-IronPort-AV: E=Sophos;i="6.25,193,1779174000"; d="scan'208";a="85999679" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jul 2026 16:09:38 -0700 X-CSE-ConnectionGUID: OQiJ/fXOQuSFgvQnvcP3tg== X-CSE-MsgGUID: g99xHajPQoS63B3UG1PjNA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,193,1779174000"; d="scan'208";a="256803555" Received: from mcapezzu-mobl1.amr.corp.intel.com (HELO adixit-MOBL3.intel.com) ([10.125.38.25]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jul 2026 16:09:37 -0700 Date: Wed, 29 Jul 2026 16:09:36 -0700 Message-ID: <87h5lh75qn.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Matt Roper Cc: , Gustavo Sousa Subject: Re: [PATCH v3 1/2] drm/xe/mcr: Take vcs1/vecs1 into account for first media slice In-Reply-To: <20260728205710.GA8279@mdroper-desk1.amr.corp.intel.com> References: <20260727172712.2877706-1-ashutosh.dixit@intel.com> <20260727172712.2877706-2-ashutosh.dixit@intel.com> <20260728205710.GA8279@mdroper-desk1.amr.corp.intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Tue, 28 Jul 2026 13:57:10 -0700, Matt Roper wrote: > > On Mon, Jul 27, 2026 at 10:27:11AM -0700, Ashutosh Dixit wrote: > > vcs1 and vecs1 may also be present on the first media slice, so take > > vcs1/vecs1 also into account when determining if the first media slice is > > absent. > > > > Bspec: 67103, 77977 > > > > Cc: Gustavo Sousa > > Cc: Matt Roper > > Signed-off-by: Ashutosh Dixit > > --- > > v2: Bug fix > > v3: Fix for BMG (Matt Roper) > > --- > > drivers/gpu/drm/xe/xe_gt_mcr.c | 8 ++++++-- > > 1 file changed, 6 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c > > index 9799ffadf85d2..8beb4006cd891 100644 > > --- a/drivers/gpu/drm/xe/xe_gt_mcr.c > > +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c > > @@ -452,11 +452,15 @@ static void init_steering_dss(struct xe_gt *gt) > > > > static void init_steering_oaddrm(struct xe_gt *gt) > > { > > + u64 hwe_mask = XE_HW_ENGINE_VCS0 | XE_HW_ENGINE_VECS0; > > + > > + if (MEDIA_VERx100(gt_to_xe(gt)) >= 3500) > > This will work as a short-term bandaid, but fundamentally the media > configuration isn't really a case where "old platforms were always 1/1/1 > and new platforms will probably always be 2/2/2." It's something that > can easily vary platform-by-platform or even SKU-by-SKU (e.g., bspec > 70819 still shows some what was originally planned in the past for > different SKUs of a platform, even though that platform eventually > settled on something simpler). If I recall correctly, there were also > configurations like 2/1/1 used on older platforms like DG2, but we > didn't need to worry about SCMI or OADDRM steering for MCR purposes on > those platforms so it just never came up in the code. > > I'm okay landing this patch as a short-term fix for NVL and CRI, but we > should add a TODO comment or something indicating that we really should > move the "VD per SCMI" and "VE per SCMI" values into our media > descriptors so that we can easily pick the appropriate config on a > per-release / per-SKU manner to ensure we think about it on a > release-by-release basis when enabling new platforms and IP versions in > the future. Thanks Matt, I have added the TODO in v4, I prefer to merge this for now as a short-term fix for NVL and CRI. Thanks. > > > + hwe_mask |= XE_HW_ENGINE_VCS1 | XE_HW_ENGINE_VECS1; > > /* > > * First instance is only terminated if the entire first media slice > > - * is absent (i.e., no VCS0 or VECS0). > > + * is absent (i.e., no engines in hwe_mask). > > */ > > - if (gt->info.engine_mask & (XE_HW_ENGINE_VCS0 | XE_HW_ENGINE_VECS0)) > > + if (gt->info.engine_mask & hwe_mask) > > gt->steering[OADDRM].group_target = 0; > > else > > gt->steering[OADDRM].group_target = 1; > > -- > > 2.54.0 > > > > -- > Matt Roper > Graphics Software Engineer > Linux GPU Platform Enablement > Intel Corporation