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Wed, 03 Jun 2026 08:35:56 -0700 (PDT) Received: from draig.lan ([185.124.0.195]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4601f2dcb13sm7703608f8f.2.2026.06.03.08.35.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jun 2026 08:35:56 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 1DEE45F8A6; Wed, 03 Jun 2026 16:35:55 +0100 (BST) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Richard Henderson Cc: qemu-devel@nongnu.org Subject: Re: [PATCH] target/arm: replace cp_regs hashtable lookup with direct array index In-Reply-To: <17132c4d-c523-4459-b1aa-236c9046e2b6@linaro.org> (Richard Henderson's message of "Wed, 3 Jun 2026 07:22:58 -0700") References: <20260518-enhance_arm_gdb_get_sysreg_performance-v1-1-f0a5b22003c0@gmail.com> <877boguk7a.fsf@draig.linaro.org> <17132c4d-c523-4459-b1aa-236c9046e2b6@linaro.org> User-Agent: mu4e 1.14.1; emacs 30.1 Date: Wed, 03 Jun 2026 16:35:55 +0100 Message-ID: <87h5njtz50.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Richard Henderson writes: > On 6/3/26 01:00, Alex Benn=C3=A9e wrote: >>> This will not work, because each ARMCPU has separate cpreg info >>> structures, and these structures only have the lifetime of the ARMCPU >>> struct. We create and destroy these at runtime, so at some point you >>> may end up with pointers to freed memory. >> Shouldn't it be the same set for each CPU though? > > I have thought for some time that the cpregs should be stored on the > class, not the instance, so that these structures are shared, but it's > non-trivial. IIRC there are also some places where the list isn't complete until realize time (I think for things like the GIC system registers). > > r~ --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro