Re: [PATCH] drm/xe/xe3: Apply Wa_16029380221 to media

[Gustavo Sousa <gustavo.sousa@intel.com>]

Nitin Gote <nitin.r.gote@intel.com> writes:

> Apply Wa_16029380221 to Xe3p_LPM.
>
> The Xe3p_LPM media page walker is hard-wired NonCoherent and cannot
> observe CPU:WB cached page table data. Force page tables to CPU:WC
> by clearing has_cached_pt when MEDIA_VERSION(3500) is detected.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_device.c     | 9 +++++++++
>  drivers/gpu/drm/xe/xe_wa_oob.rules | 1 +
>  2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index d224861b6f6f..8a6f494e11d5 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -948,6 +948,15 @@ int xe_device_probe(struct xe_device *xe)
>  			return err;
>  	}
>  
> +	/*
> +	 * Wa_16029380221: Xe3p_LPM media page walker is hard-wired
> +	 * NonCoherent, so page tables must use CPU:WC (uncached) to
> +	 * be visible to the media engine regardless of stepping.
> +	 */
> +	for_each_gt(gt, xe, id)
> +		if (XE_GT_WA(gt, 16029380221))
> +			xe->info.has_cached_pt = false;
> +

This will also disable the feature for the primary GT. Do we really
want/need that?

I wonder if we should change this setting to be a per-GT one instead of
global to the device.  Perhaps one problem would be page tables shared
between media and primary GT.  Is that a possibility?

--
Gustavo Sousa

>  	for_each_tile(tile, xe, id) {
>  		err = xe_ggtt_init_early(tile->mem.ggtt);
>  		if (err)
> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> index f8a185103b80..9027365f0043 100644
> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> @@ -65,3 +65,4 @@
>  
>  14025883347	MEDIA_VERSION_RANGE(1301, 3503)
>  		GRAPHICS_VERSION_RANGE(2004, 3005)
> +16029380221	MEDIA_VERSION(3500)
> -- 
> 2.50.1