From: Thomas Gleixner <tglx@linutronix.de>
To: Shrikanth Hegde <sshegde@linux.ibm.com>,
LKML <linux-kernel@vger.kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>,
Gabriele Monaco <gmonaco@redhat.com>,
Mathieu Desnoyers <mathieu.desnoyers@efficios.com>,
Michael Jeanson <mjeanson@efficios.com>,
Jens Axboe <axboe@kernel.dk>,
"Paul E. McKenney" <paulmck@kernel.org>,
"Gautham R. Shenoy" <gautham.shenoy@amd.com>,
Florian Weimer <fweimer@redhat.com>,
Tim Chen <tim.c.chen@intel.com>,
Yury Norov <yury.norov@gmail.com>
Subject: Re: [patch V3 00/20] sched: Rewrite MM CID management
Date: Sat, 01 Nov 2025 13:27:59 +0100 [thread overview]
Message-ID: <87h5vex7hs.ffs@tglx> (raw)
In-Reply-To: <3f7ec825-7e85-499f-bc44-1fcda0a862ae@linux.ibm.com>
On Sat, Nov 01 2025 at 13:26, Shrikanth Hegde wrote:
> On 11/1/25 1:06 AM, Thomas Gleixner wrote:
>> On Thu, Oct 30 2025 at 12:10, Shrikanth Hegde wrote:
>>>> I am running into crash at boot on power10 pseries.
>>>> Thought of putting it here first. Me trying to figure out why.
>>>>
>>>> I am using your tree.
>>>> git://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git
>>
>> Can you update and revalidate? There are a couple of fixes there though
>> I don't know how they would be related.
>
> Tried with latest. It boots fine with NR_CPUS=8192.
Thanks a lot!
next prev parent reply other threads:[~2025-11-01 12:28 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-29 13:08 [patch V3 00/20] sched: Rewrite MM CID management Thomas Gleixner
2025-10-29 13:08 ` [patch V3 01/20] sched/mmcid: Revert the complex " Thomas Gleixner
2025-10-29 13:08 ` [patch V3 02/20] sched/mmcid: Use proper data structures Thomas Gleixner
2025-10-29 15:31 ` Mathieu Desnoyers
2025-10-29 13:08 ` [patch V3 03/20] sched/mmcid: Cacheline align MM CID storage Thomas Gleixner
2025-10-29 15:39 ` Mathieu Desnoyers
2025-10-29 21:09 ` Thomas Gleixner
2025-10-30 14:15 ` Mathieu Desnoyers
2025-10-29 13:09 ` [patch V3 04/20] sched: Fixup whitespace damage Thomas Gleixner
2025-10-29 15:42 ` Mathieu Desnoyers
2025-10-29 21:11 ` Thomas Gleixner
2025-10-29 13:09 ` [patch V3 05/20] sched/mmcid: Move scheduler code out of global header Thomas Gleixner
2025-10-29 15:43 ` Mathieu Desnoyers
2025-10-29 13:09 ` [patch V3 06/20] sched/mmcid: Prevent pointless work in mm_update_cpus_allowed() Thomas Gleixner
2025-10-29 15:45 ` Mathieu Desnoyers
2025-10-29 13:09 ` [patch V3 07/20] cpumask: Introduce cpumask_weighted_or() Thomas Gleixner
2025-10-29 15:49 ` Mathieu Desnoyers
2025-11-03 9:15 ` Shrikanth Hegde
2025-11-03 13:29 ` Thomas Gleixner
2025-11-10 16:11 ` Peter Zijlstra
2025-11-10 16:42 ` Mathieu Desnoyers
2025-10-29 13:09 ` [patch V3 08/20] sched/mmcid: Use cpumask_weighted_or() Thomas Gleixner
2025-10-29 15:51 ` Mathieu Desnoyers
2025-10-29 13:09 ` [patch V3 09/20] cpumask: Cache num_possible_cpus() Thomas Gleixner
2025-10-29 15:54 ` Mathieu Desnoyers
2025-10-29 21:11 ` Thomas Gleixner
2025-11-01 22:59 ` Thomas Gleixner
2025-11-03 10:06 ` Shrikanth Hegde
2025-11-03 13:28 ` Thomas Gleixner
2025-10-29 13:09 ` [patch V3 10/20] sched/mmcid: Convert mm CID mask to a bitmap Thomas Gleixner
2025-10-30 13:59 ` Mathieu Desnoyers
2025-10-29 13:09 ` [patch V3 11/20] signal: Move MMCID exit out of sighand lock Thomas Gleixner
2025-10-29 13:09 ` [patch V3 12/20] sched/mmcid: Move initialization out of line Thomas Gleixner
2025-10-30 14:02 ` Mathieu Desnoyers
2025-10-29 13:09 ` [patch V3 13/20] sched/mmcid: Provide precomputed maximal value Thomas Gleixner
2025-10-30 14:23 ` Mathieu Desnoyers
2025-10-31 15:06 ` Thomas Gleixner
2025-10-31 15:14 ` Mathieu Desnoyers
2025-10-29 13:09 ` [patch V3 14/20] sched/mmcid: Serialize sched_mm_cid_fork()/exit() with a mutex Thomas Gleixner
2025-10-30 14:25 ` Mathieu Desnoyers
2025-10-29 13:09 ` [patch V3 15/20] sched/mmcid: Introduce per task/CPU ownership infrastrcuture Thomas Gleixner
2025-10-30 14:45 ` Mathieu Desnoyers
2025-10-29 13:09 ` [patch V3 16/20] sched/mmcid: Provide new scheduler CID mechanism Thomas Gleixner
2025-10-30 15:09 ` Mathieu Desnoyers
2025-10-29 13:09 ` [patch V3 17/20] sched/mmcid: Provide CID ownership mode fixup functions Thomas Gleixner
2025-10-30 15:51 ` Mathieu Desnoyers
2025-10-31 16:54 ` Thomas Gleixner
2025-10-31 19:15 ` Mathieu Desnoyers
2025-10-29 13:09 ` [patch V3 18/20] irqwork: Move data struct to a types header Thomas Gleixner
2025-10-30 15:52 ` Mathieu Desnoyers
2025-10-29 13:09 ` [patch V3 19/20] sched/mmcid: Implement deferred mode change Thomas Gleixner
2025-10-30 15:56 ` Mathieu Desnoyers
2025-10-29 13:09 ` [patch V3 20/20] sched/mmcid: Switch over to the new mechanism Thomas Gleixner
2025-10-30 16:07 ` Mathieu Desnoyers
2025-10-31 16:57 ` Thomas Gleixner
2025-10-31 19:17 ` Mathieu Desnoyers
2025-11-24 12:10 ` Mark Brown
2025-11-24 12:27 ` Florian Weimer
2025-11-24 13:28 ` Mark Brown
2025-10-30 5:00 ` [patch V3 00/20] sched: Rewrite MM CID management Shrikanth Hegde
2025-10-30 6:40 ` Shrikanth Hegde
2025-10-31 19:36 ` Thomas Gleixner
2025-11-01 7:56 ` Shrikanth Hegde
2025-11-01 12:27 ` Thomas Gleixner [this message]
2025-11-10 17:09 ` Gabriele Monaco
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