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Thu, 21 Aug 2025 16:00:34 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: faa70681-7ea7-11f0-b898-0df219b8e170 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=QFup0kiVnFUPYRgyQo3J9GZ/bZ0kUJW9LY9l8ipTxPD6+ENCXC6MuwDIsmgp/fYtOfx2QDhgOEU9LZy7R/FHnCsF3RhDHV3eQMY7uS2KsAJZD8SORoiJg7dqX5fND9PnnWD1gv4GeCI8a29ISS50Yw9M5C8VpqgHy+j8CQM8f8JFf+Y6ZYaDToHDWyx4NHYO8Qszp0FE0bgbwJhT5ku4bXN6sFSJxWxRPlCvvJhZlOexEqGzSH4CXxZb5ndEsgP5+5bX3s/lCCtIyyKK+P9X0DnpdOSv37+JG3Z7TxElcEdBa7bejqEdiU0cWCdlnf/v2wqw/hQEhY6+rUJa/3U75Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: GV1PR03MB10456.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: d15c5df9-cd96-4733-254c-08dde0cbdd17 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Aug 2025 16:00:34.8505 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: dF2HXbAEEG14cP7J+1+3L01RqICtti57X1o2bO3Mmzwkk//UBLuBGHXeiLVMcZaj2he43JRR0GWP6oY0wMW4S6Oh23J3XKgDDuZfPVuht/c= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAVPR03MB9164 Hi, Leonid Komarianskyi writes: > Currently, many common functions perform the same operations to calculate > GIC register addresses. This patch consolidates the similar code into > a separate helper function to improve maintainability and reduce duplicat= ion. > This refactoring also simplifies the implementation of eSPI support in fu= ture > changes. > > Signed-off-by: Leonid Komarianskyi Reviewed-by: Volodymyr Babchuk > > --- > Changes in V2: > - no changes > --- > xen/arch/arm/gic-v3.c | 99 ++++++++++++++++++++++------------ > xen/arch/arm/include/asm/irq.h | 1 + > 2 files changed, 67 insertions(+), 33 deletions(-) > > diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c > index cd3e1acf79..8fd78aba44 100644 > --- a/xen/arch/arm/gic-v3.c > +++ b/xen/arch/arm/gic-v3.c > @@ -445,17 +445,62 @@ static void gicv3_dump_state(const struct vcpu *v) > } > } > =20 > +static void __iomem *get_addr_by_offset(struct irq_desc *irqd, u32 offse= t) > +{ > + switch ( irqd->irq ) > + { > + case 0 ... (NR_GIC_LOCAL_IRQS - 1): > + switch ( offset ) > + { > + case GICD_ISENABLER: > + case GICD_ICENABLER: > + case GICD_ISPENDR: > + case GICD_ICPENDR: > + case GICD_ISACTIVER: > + case GICD_ICACTIVER: > + return (GICD_RDIST_SGI_BASE + offset); > + case GICD_ICFGR: > + return (GICD_RDIST_SGI_BASE + GICR_ICFGR1); > + case GICD_IPRIORITYR: > + return (GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + irqd->irq); > + default: > + break; > + } > + case NR_GIC_LOCAL_IRQS ... SPI_MAX_INTID: > + switch ( offset ) > + { > + case GICD_ISENABLER: > + case GICD_ICENABLER: > + case GICD_ISPENDR: > + case GICD_ICPENDR: > + case GICD_ISACTIVER: > + case GICD_ICACTIVER: > + return (GICD + offset + (irqd->irq / 32) * 4); > + case GICD_ICFGR: > + return (GICD + GICD_ICFGR + (irqd->irq / 16) * 4); > + case GICD_IROUTER: > + return (GICD + GICD_IROUTER + irqd->irq * 8); > + case GICD_IPRIORITYR: > + return (GICD + GICD_IPRIORITYR + irqd->irq); > + default: > + break; > + } > + default: > + break; > + } > + > + /* Something went wrong, we shouldn't be able to reach here */ > + panic("Invalid offset 0x%x for IRQ#%d", offset, irqd->irq); > + > + return NULL; > +} > + > static void gicv3_poke_irq(struct irq_desc *irqd, u32 offset, bool wait_= for_rwp) > { > u32 mask =3D 1U << (irqd->irq % 32); > - void __iomem *base; > - > - if ( irqd->irq < NR_GIC_LOCAL_IRQS ) > - base =3D GICD_RDIST_SGI_BASE; > - else > - base =3D GICD; > + void __iomem *addr =3D get_addr_by_offset(irqd, offset); > =20 > - writel_relaxed(mask, base + offset + (irqd->irq / 32) * 4); > + writel_relaxed(mask, addr); > =20 > if ( wait_for_rwp ) > gicv3_wait_for_rwp(irqd->irq); > @@ -463,15 +508,9 @@ static void gicv3_poke_irq(struct irq_desc *irqd, u3= 2 offset, bool wait_for_rwp) > =20 > static bool gicv3_peek_irq(struct irq_desc *irqd, u32 offset) > { > - void __iomem *base; > - unsigned int irq =3D irqd->irq; > - > - if ( irq >=3D NR_GIC_LOCAL_IRQS) > - base =3D GICD + (irq / 32) * 4; > - else > - base =3D GICD_RDIST_SGI_BASE; > + void __iomem *addr =3D get_addr_by_offset(irqd, offset); > =20 > - return !!(readl(base + offset) & (1U << (irq % 32))); > + return !!(readl(addr) & (1U << (irqd->irq % 32))); > } > =20 > static void gicv3_unmask_irq(struct irq_desc *irqd) > @@ -558,30 +597,26 @@ static inline uint64_t gicv3_mpidr_to_affinity(int = cpu) > static void gicv3_set_irq_type(struct irq_desc *desc, unsigned int type) > { > uint32_t cfg, actual, edgebit; > - void __iomem *base; > - unsigned int irq =3D desc->irq; > + void __iomem *addr; > =20 > /* SGI's are always edge-triggered not need to call GICD_ICFGR0 */ > - ASSERT(irq >=3D NR_GIC_SGI); > + ASSERT(desc->irq >=3D NR_GIC_SGI); > =20 > spin_lock(&gicv3.lock); > =20 > - if ( irq >=3D NR_GIC_LOCAL_IRQS) > - base =3D GICD + GICD_ICFGR + (irq / 16) * 4; > - else > - base =3D GICD_RDIST_SGI_BASE + GICR_ICFGR1; > + addr =3D get_addr_by_offset(desc, GICD_ICFGR); > =20 > - cfg =3D readl_relaxed(base); > + cfg =3D readl_relaxed(addr); > =20 > - edgebit =3D 2u << (2 * (irq % 16)); > + edgebit =3D 2u << (2 * (desc->irq % 16)); > if ( type & IRQ_TYPE_LEVEL_MASK ) > cfg &=3D ~edgebit; > else if ( type & IRQ_TYPE_EDGE_BOTH ) > cfg |=3D edgebit; > =20 > - writel_relaxed(cfg, base); > + writel_relaxed(cfg, addr); > =20 > - actual =3D readl_relaxed(base); > + actual =3D readl_relaxed(addr); > if ( ( cfg & edgebit ) ^ ( actual & edgebit ) ) > { > printk(XENLOG_WARNING "GICv3: WARNING: " > @@ -600,15 +635,12 @@ static void gicv3_set_irq_type(struct irq_desc *des= c, unsigned int type) > static void gicv3_set_irq_priority(struct irq_desc *desc, > unsigned int priority) > { > - unsigned int irq =3D desc->irq; > + void __iomem *addr; > =20 > spin_lock(&gicv3.lock); > =20 > - /* Set priority */ > - if ( irq < NR_GIC_LOCAL_IRQS ) > - writeb_relaxed(priority, GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 = + irq); > - else > - writeb_relaxed(priority, GICD + GICD_IPRIORITYR + irq); > + addr =3D get_addr_by_offset(desc, GICD_IPRIORITYR); > + writeb_relaxed(priority, addr); > =20 > spin_unlock(&gicv3.lock); > } > @@ -1273,6 +1305,7 @@ static void gicv3_irq_set_affinity(struct irq_desc = *desc, const cpumask_t *mask) > { > unsigned int cpu; > uint64_t affinity; > + void __iomem *addr =3D get_addr_by_offset(desc, GICD_IROUTER); > =20 > ASSERT(!cpumask_empty(mask)); > =20 > @@ -1284,7 +1317,7 @@ static void gicv3_irq_set_affinity(struct irq_desc = *desc, const cpumask_t *mask) > affinity &=3D ~GICD_IROUTER_SPI_MODE_ANY; > =20 > if ( desc->irq >=3D NR_GIC_LOCAL_IRQS ) > - writeq_relaxed_non_atomic(affinity, (GICD + GICD_IROUTER + desc-= >irq * 8)); > + writeq_relaxed_non_atomic(affinity, addr); > =20 > spin_unlock(&gicv3.lock); > } > diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/asm/ir= q.h > index fce7e42a33..5bc6475eb4 100644 > --- a/xen/arch/arm/include/asm/irq.h > +++ b/xen/arch/arm/include/asm/irq.h > @@ -29,6 +29,7 @@ struct arch_irq_desc { > */ > #define NR_IRQS 1024 > =20 > +#define SPI_MAX_INTID 1019 > #define LPI_OFFSET 8192 > =20 > /* LPIs are always numbered starting at 8192, so 0 is a good invalid cas= e. */ --=20 WBR, Volodymyr=