From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D08D3C433F5 for ; Mon, 28 Mar 2022 11:07:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5E35610E176; Mon, 28 Mar 2022 11:07:34 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 05AAE10E176 for ; Mon, 28 Mar 2022 11:07:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648465653; x=1680001653; h=from:to:subject:in-reply-to:references:date:message-id: mime-version:content-transfer-encoding; bh=Lk/hNkyEeaS7sd2K7W0OMKIzXxdL5fgxFh2kNIjMdP4=; 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charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Intel-gfx] [PATCH 08/13] drm/i915: Split out dg2_crtc_compute_clock() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, 25 Mar 2022, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > DG2 doesn't currently used the shared_dpll stuff so let's just > split it out from hsw_crtc_compute_clock() entirely. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_dpll.c | 22 ++++++++++++++++++---- > 1 file changed, 18 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/= i915/display/intel_dpll.c > index 7960f1d52eaa..bc59efe18e89 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll.c > @@ -938,9 +938,6 @@ static int hsw_crtc_compute_clock(struct intel_atomic= _state *state, > intel_get_crtc_new_encoder(state, crtc_state); > int ret; >=20=20 > - if (IS_DG2(dev_priv)) > - return intel_mpllb_calc_state(crtc_state, encoder); > - > if (DISPLAY_VER(dev_priv) < 11 && > intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) > return 0; > @@ -956,6 +953,17 @@ static int hsw_crtc_compute_clock(struct intel_atomi= c_state *state, > return 0; > } >=20=20 > +static int dg2_crtc_compute_clock(struct intel_atomic_state *state, > + struct intel_crtc *crtc) > +{ > + struct intel_crtc_state *crtc_state =3D > + intel_atomic_get_new_crtc_state(state, crtc); > + struct intel_encoder *encoder =3D > + intel_get_crtc_new_encoder(state, crtc_state); > + > + return intel_mpllb_calc_state(crtc_state, encoder); > +} > + > static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor) > { > return dpll->m < factor * dpll->n; > @@ -1362,6 +1370,10 @@ static int i8xx_crtc_compute_clock(struct intel_at= omic_state *state, > return 0; > } >=20=20 > +static const struct intel_dpll_funcs dg2_dpll_funcs =3D { > + .crtc_compute_clock =3D dg2_crtc_compute_clock, > +}; > + > static const struct intel_dpll_funcs hsw_dpll_funcs =3D { > .crtc_compute_clock =3D hsw_crtc_compute_clock, > }; > @@ -1418,7 +1430,9 @@ int intel_dpll_crtc_compute_clock(struct intel_atom= ic_state *state, > void > intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv) > { > - if (DISPLAY_VER(dev_priv) >=3D 9 || HAS_DDI(dev_priv)) > + if (IS_DG2(dev_priv)) > + dev_priv->dpll_funcs =3D &dg2_dpll_funcs; > + else if (DISPLAY_VER(dev_priv) >=3D 9 || HAS_DDI(dev_priv)) > dev_priv->dpll_funcs =3D &hsw_dpll_funcs; > else if (HAS_PCH_SPLIT(dev_priv)) > dev_priv->dpll_funcs =3D &ilk_dpll_funcs; --=20 Jani Nikula, Intel Open Source Graphics Center