Re: [Intel-gfx] [PATCH] drm/i915/gt: Trace placement of timeline HWSP

[Mika Kuoppala <mika.kuoppala@linux.intel.com>]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Track the position of the HWSP for each timeline.
>
> References: https://gitlab.freedesktop.org/drm/intel/-/issues/2169
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_timeline.c    |  7 +++++++
>  drivers/gpu/drm/i915/gt/selftest_timeline.c | 13 ++++++++-----
>  2 files changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
> index 4546284fede1..46d20f5f3ddc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_timeline.c
> +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
> @@ -73,6 +73,8 @@ hwsp_alloc(struct intel_timeline *timeline, unsigned int *cacheline)
>  			return vma;
>  		}
>  
> +		GT_TRACE(timeline->gt, "new HWSP allocated\n");
> +
>  		vma->private = hwsp;
>  		hwsp->gt = timeline->gt;
>  		hwsp->vma = vma;
> @@ -327,6 +329,8 @@ int intel_timeline_pin(struct intel_timeline *tl)
>  	tl->hwsp_offset =
>  		i915_ggtt_offset(tl->hwsp_ggtt) +
>  		offset_in_page(tl->hwsp_offset);
> +	GT_TRACE(tl->gt, "timeline:%llx using HWSP offset:%x\n",
> +		 tl->fence_context, tl->hwsp_offset);

Regarless of that the coffee is starting to sink in,
I am somewhat uneasy with the whole hwsp_offset being
used both as an offset in page and then in offset in ggtt.

Further, my paranoia is enhanced as if the race
to pin gets losing side, the hwsp_offset linger
to an stale(ish) offset.

But for tracing,
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
-Mika

>  
>  	cacheline_acquire(tl->hwsp_cacheline);
>  	if (atomic_fetch_inc(&tl->pin_count)) {
> @@ -434,6 +438,7 @@ __intel_timeline_get_seqno(struct intel_timeline *tl,
>  	int err;
>  
>  	might_lock(&tl->gt->ggtt->vm.mutex);
> +	GT_TRACE(tl->gt, "timeline:%llx wrapped\n", tl->fence_context);
>  
>  	/*
>  	 * If there is an outstanding GPU reference to this cacheline,
> @@ -497,6 +502,8 @@ __intel_timeline_get_seqno(struct intel_timeline *tl,
>  		memset(vaddr + tl->hwsp_offset, 0, CACHELINE_BYTES);
>  
>  	tl->hwsp_offset += i915_ggtt_offset(vma);
> +	GT_TRACE(tl->gt, "timeline:%llx using HWSP offset:%x\n",
> +		 tl->fence_context, tl->hwsp_offset);
>  
>  	cacheline_acquire(cl);
>  	tl->hwsp_cacheline = cl;
> diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> index fcdee951579b..fb5b7d3498a6 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> @@ -562,8 +562,9 @@ static int live_hwsp_engine(void *arg)
>  		struct intel_timeline *tl = timelines[n];
>  
>  		if (!err && *tl->hwsp_seqno != n) {
> -			pr_err("Invalid seqno stored in timeline %lu, found 0x%x\n",
> -			       n, *tl->hwsp_seqno);
> +			pr_err("Invalid seqno stored in timeline %lu @ %x, found 0x%x\n",
> +			       n, tl->hwsp_offset, *tl->hwsp_seqno);
> +			GEM_TRACE_DUMP();
>  			err = -EINVAL;
>  		}
>  		intel_timeline_put(tl);
> @@ -633,8 +634,9 @@ static int live_hwsp_alternate(void *arg)
>  		struct intel_timeline *tl = timelines[n];
>  
>  		if (!err && *tl->hwsp_seqno != n) {
> -			pr_err("Invalid seqno stored in timeline %lu, found 0x%x\n",
> -			       n, *tl->hwsp_seqno);
> +			pr_err("Invalid seqno stored in timeline %lu @ %x, found 0x%x\n",
> +			       n, tl->hwsp_offset, *tl->hwsp_seqno);
> +			GEM_TRACE_DUMP();
>  			err = -EINVAL;
>  		}
>  		intel_timeline_put(tl);
> @@ -965,8 +967,9 @@ static int live_hwsp_recycle(void *arg)
>  			}
>  
>  			if (*tl->hwsp_seqno != count) {
> -				pr_err("Invalid seqno stored in timeline %lu, found 0x%x\n",
> +				pr_err("Invalid seqno stored in timeline %lu @ tl->hwsp_offset, found 0x%x\n",
>  				       count, *tl->hwsp_seqno);
> +				GEM_TRACE_DUMP();
>  				err = -EINVAL;
>  			}
>  
> -- 
> 2.20.1
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