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References: <20181025144644.15464-1-cota@braap.org>
	<20181025144644.15464-11-cota@braap.org>
From: Alex =?utf-8?Q?Benn=C3=A9e?= <alex.bennee@linaro.org>
In-reply-to: <20181025144644.15464-11-cota@braap.org>
Date: Wed, 31 Oct 2018 11:43:54 +0000
Message-ID: <87h8h28hol.fsf@linaro.org>
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Subject: Re: [Qemu-devel] [RFC v4 11/71] m68k: convert to
 helper_cpu_halted_set
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To: "Emilio G. Cota" <cota@braap.org>
Cc: qemu-devel@nongnu.org, Paolo Bonzini <pbonzini@redhat.com>, Richard Henderson <richard.henderson@linaro.org>, Laurent Vivier <laurent@vivier.eu>


Emilio G. Cota <cota@braap.org> writes:

> Cc: Laurent Vivier <laurent@vivier.eu>
> Signed-off-by: Emilio G. Cota <cota@braap.org>

Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>

> ---
>  target/m68k/translate.c | 9 ++++-----
>  1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/target/m68k/translate.c b/target/m68k/translate.c
> index ae3651b867..d55e707cf6 100644
> --- a/target/m68k/translate.c
> +++ b/target/m68k/translate.c
> @@ -43,7 +43,6 @@
>  #undef DEFO32
>  #undef DEFO64
>
> -static TCGv_i32 cpu_halted;
>  static TCGv_i32 cpu_exception_index;
>
>  static char cpu_reg_names[2 * 8 * 3 + 5 * 4];
> @@ -79,9 +78,6 @@ void m68k_tcg_init(void)
>  #undef DEFO32
>  #undef DEFO64
>
> -    cpu_halted =3D tcg_global_mem_new_i32(cpu_env,
> -                                        -offsetof(M68kCPU, env) +
> -                                        offsetof(CPUState, halted), "HAL=
TED");
>      cpu_exception_index =3D tcg_global_mem_new_i32(cpu_env,
>                                                   -offsetof(M68kCPU, env)=
 +
>                                                   offsetof(CPUState, exce=
ption_index),
> @@ -4637,6 +4633,7 @@ DISAS_INSN(halt)
>  DISAS_INSN(stop)
>  {
>      uint16_t ext;
> +    TCGv_i32 tmp;
>
>      if (IS_USER(s)) {
>          gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
> @@ -4646,7 +4643,9 @@ DISAS_INSN(stop)
>      ext =3D read_im16(env, s);
>
>      gen_set_sr_im(s, ext, 0);
> -    tcg_gen_movi_i32(cpu_halted, 1);
> +    tmp =3D tcg_const_i32(1);
> +    gen_helper_cpu_halted_set(cpu_env, tmp);
> +    tcg_temp_free_i32(tmp);
>      gen_exception(s, s->pc, EXCP_HLT);
>  }


--
Alex Benn=C3=A9e