From: Jani Nikula <jani.nikula@linux.intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 11/16] drm/i915: Do not initialize display core when display is disabled
Date: Mon, 22 Oct 2018 11:39:24 +0300 [thread overview]
Message-ID: <87h8hefk8z.fsf@intel.com> (raw)
In-Reply-To: <20181012215218.5119-11-jose.souza@intel.com>
On Fri, 12 Oct 2018, José Roberto de Souza <jose.souza@intel.com> wrote:
> With display disabled, driver don't need to enable any power well
> or load the DMC firmware.
>
> The only thing that *_display_core_init will do when display is
> disabled is call intel_pch_reset_handshake(), so PCH handshake
> will be unset and in counterpart *_display_core_uninit() will
> only disable DC.
>
> The power wells enabled by BIOS during boot will be disabled in
> futher patch.
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 56 ++++++++++++++++---------
> 1 file changed, 36 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 3b2588a377a9..8b1c4d0db0af 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -3285,6 +3285,9 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
> /* enable PCH reset handshake */
> intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
>
> + if (!INTEL_INFO(dev_priv)->num_pipes)
> + return;
> +
> /* enable PG1 and Misc I/O */
> mutex_lock(&power_domains->lock);
>
> @@ -3296,8 +3299,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
>
> mutex_unlock(&power_domains->lock);
>
> - if (INTEL_INFO(dev_priv)->num_pipes)
> - skl_init_cdclk(dev_priv);
> + skl_init_cdclk(dev_priv);
Please do the series in a way that doesn't need to undo stuff you add
earlier in the series.
>
> gen9_dbuf_enable(dev_priv);
>
> @@ -3312,10 +3314,12 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>
> + if (!INTEL_INFO(dev_priv)->num_pipes)
> + return;
> +
> gen9_dbuf_disable(dev_priv);
>
> - if (INTEL_INFO(dev_priv)->num_pipes)
> - skl_uninit_cdclk(dev_priv);
> + skl_uninit_cdclk(dev_priv);
>
> /* The spec doesn't call for removing the reset handshake flag */
> /* disable PG1 and Misc I/O */
> @@ -3352,6 +3356,9 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
> */
> intel_pch_reset_handshake(dev_priv, false);
>
> + if (!INTEL_INFO(dev_priv)->num_pipes)
> + return;
> +
> /* Enable PG1 */
> mutex_lock(&power_domains->lock);
>
> @@ -3360,8 +3367,7 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
>
> mutex_unlock(&power_domains->lock);
>
> - if (INTEL_INFO(dev_priv)->num_pipes)
> - bxt_init_cdclk(dev_priv);
> + bxt_init_cdclk(dev_priv);
>
> gen9_dbuf_enable(dev_priv);
>
> @@ -3376,10 +3382,12 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>
> + if (!INTEL_INFO(dev_priv)->num_pipes)
> + return;
> +
> gen9_dbuf_disable(dev_priv);
>
> - if (INTEL_INFO(dev_priv)->num_pipes)
> - bxt_uninit_cdclk(dev_priv);
> + bxt_uninit_cdclk(dev_priv);
>
> /* The spec doesn't call for removing the reset handshake flag */
>
> @@ -3475,6 +3483,9 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
> /* 1. Enable PCH Reset Handshake */
> intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
>
> + if (!INTEL_INFO(dev_priv)->num_pipes)
> + return;
> +
> /* 2. Enable Comp */
> val = I915_READ(CHICKEN_MISC_2);
> val &= ~CNL_COMP_PWR_DOWN;
> @@ -3502,8 +3513,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
> mutex_unlock(&power_domains->lock);
>
> /* 5. Enable CD clock */
> - if (INTEL_INFO(dev_priv)->num_pipes)
> - cnl_init_cdclk(dev_priv);
> + cnl_init_cdclk(dev_priv);
>
> /* 6. Enable DBUF */
> gen9_dbuf_enable(dev_priv);
> @@ -3520,14 +3530,16 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>
> - /* 1. Disable all display engine functions -> aready done */
> + if (!INTEL_INFO(dev_priv)->num_pipes)
> + return;
> +
> + /* 1. Disable all display engine functions -> already done */
>
> /* 2. Disable DBUF */
> gen9_dbuf_disable(dev_priv);
>
> /* 3. Disable CD clock */
> - if (INTEL_INFO(dev_priv)->num_pipes)
> - cnl_uninit_cdclk(dev_priv);
> + cnl_uninit_cdclk(dev_priv);
>
> /*
> * 4. Disable Power Well 1 (PG1).
> @@ -3560,6 +3572,9 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> /* 1. Enable PCH reset handshake. */
> intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
>
> + if (!INTEL_INFO(dev_priv)->num_pipes)
> + return;
> +
> for (port = PORT_A; port <= PORT_B; port++) {
> /* 2. Enable DDI combo PHY comp. */
> val = I915_READ(ICL_PHY_MISC(port));
> @@ -3588,8 +3603,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> mutex_unlock(&power_domains->lock);
>
> /* 5. Enable CDCLK. */
> - if (INTEL_INFO(dev_priv)->num_pipes)
> - icl_init_cdclk(dev_priv);
> + icl_init_cdclk(dev_priv);
>
> /* 6. Enable DBUF. */
> icl_dbuf_enable(dev_priv);
> @@ -3610,14 +3624,16 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>
> - /* 1. Disable all display engine functions -> aready done */
> + if (!INTEL_INFO(dev_priv)->num_pipes)
> + return;
> +
> + /* 1. Disable all display engine functions -> already done */
>
> /* 2. Disable DBUF */
> icl_dbuf_disable(dev_priv);
>
> /* 3. Disable CD clock */
> - if (INTEL_INFO(dev_priv)->num_pipes)
> - icl_uninit_cdclk(dev_priv);
> + icl_uninit_cdclk(dev_priv);
>
> /*
> * 4. Disable Power Well 1 (PG1).
> @@ -3784,11 +3800,11 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
> skl_display_core_init(dev_priv, resume);
> } else if (IS_GEN9_LP(dev_priv)) {
> bxt_display_core_init(dev_priv, resume);
> - } else if (IS_CHERRYVIEW(dev_priv)) {
> + } else if (IS_CHERRYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) {
> mutex_lock(&power_domains->lock);
> chv_phy_control_init(dev_priv);
> mutex_unlock(&power_domains->lock);
> - } else if (IS_VALLEYVIEW(dev_priv)) {
> + } else if (IS_VALLEYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) {
> mutex_lock(&power_domains->lock);
> vlv_cmnlane_wa(dev_priv);
> mutex_unlock(&power_domains->lock);
Please don't mix platform specific if ladders with display or not.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
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next prev parent reply other threads:[~2018-10-22 8:39 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-12 21:52 [PATCH 01/16] drm/i915: Properly set PCH as NOP when display is disabled José Roberto de Souza
2018-10-12 21:52 ` [PATCH 02/16] drm/i915: Move out non-display related calls from display/modeset init/cleanup José Roberto de Souza
2018-10-15 11:14 ` Chris Wilson
2018-10-15 23:51 ` Souza, Jose
2018-10-12 21:52 ` [PATCH 03/16] drm/i915: Move drm_vblank_init() to i915_load_modeset_init() José Roberto de Souza
2018-10-12 21:52 ` [PATCH 04/16] drm/i915: Move FBC init and cleanup calls to modeset functions José Roberto de Souza
2018-10-12 21:52 ` [PATCH 05/16] drm/i915: Move intel_init_ipc() call to i915_load_modeset_init() José Roberto de Souza
2018-10-12 21:52 ` [PATCH 06/16] drm/i915: Don't call modeset related functions when display is disabled José Roberto de Souza
2018-10-22 8:25 ` Jani Nikula
2018-10-22 8:37 ` Chris Wilson
2018-10-22 9:00 ` Jani Nikula
2018-10-25 17:38 ` Souza, Jose
2019-04-08 20:50 ` Chris Wilson
2019-08-24 9:51 ` Chris Wilson
2018-10-12 21:52 ` [PATCH 07/16] drm/i915: Remove redundant checks for num_pipes == 0 José Roberto de Souza
2018-10-22 8:31 ` Jani Nikula
2018-10-12 21:52 ` [PATCH 08/16] drm/i915: Keep overlay functions naming consistent José Roberto de Souza
2018-10-22 8:32 ` Jani Nikula
2018-10-12 21:52 ` [PATCH 09/16] drm/i915: Do not reset display when display is disabled José Roberto de Souza
2018-10-22 8:34 ` Jani Nikula
2018-10-12 21:52 ` [PATCH 10/16] drm/i915: Do not initialize display clocks " José Roberto de Souza
2018-10-22 8:37 ` Jani Nikula
2018-10-12 21:52 ` [PATCH 11/16] drm/i915: Do not initialize display core " José Roberto de Souza
2018-10-22 8:39 ` Jani Nikula [this message]
2018-10-12 21:52 ` [PATCH 12/16] drm/i915: Warn when display irq functions is executed " José Roberto de Souza
2018-10-22 8:40 ` Jani Nikula
2018-10-12 21:52 ` [PATCH 13/16] drm/i915: Do not print DC off mismatch state when DMC firmware in not loaded José Roberto de Souza
2018-10-15 10:58 ` Imre Deak
2018-10-16 1:31 ` Souza, Jose
2018-10-16 9:35 ` Imre Deak
2018-10-12 21:52 ` [PATCH 14/16] drm/i915: Do not turn power wells on or off when display is disabled José Roberto de Souza
2018-10-22 8:50 ` Jani Nikula
2018-10-12 21:52 ` [PATCH 15/16] drm/i915: Power down any power well left on by BIOS José Roberto de Souza
2018-10-15 11:06 ` Imre Deak
2018-10-16 0:05 ` Souza, Jose
2018-10-16 9:39 ` Imre Deak
2018-10-12 21:52 ` [PATCH 16/16] drm/i915: Guard debugfs against invalid access when display is disabled José Roberto de Souza
2018-10-22 8:52 ` Jani Nikula
2018-10-12 22:03 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/16] drm/i915: Properly set PCH as NOP " Patchwork
2018-10-12 22:07 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-10-12 22:27 ` ✓ Fi.CI.BAT: success " Patchwork
2018-10-13 2:46 ` ✓ Fi.CI.IGT: " Patchwork
2018-11-03 21:41 ` [PATCH 01/16] " Jani Nikula
2018-11-30 8:29 ` Lucas De Marchi
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