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From: Alex =?utf-8?Q?Benn=C3=A9e?= <alex.bennee@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-arm@nongnu.org, Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v2 20/32] arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
In-reply-to: <d6f98bba-04ca-80f6-1fad-cfed416f4127@linaro.org>
Date: Thu, 22 Feb 2018 17:23:54 +0000
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Richard Henderson <richard.henderson@linaro.org> writes:

> On 02/08/2018 09:31 AM, Alex Benn=C3=A9e wrote:
>> +            maxpasses =3D hp ? (is_q ? 8 : 4) : (is_q ? 4 : 2);
>
>   (8 << is_q) >> size
>
> ?

Hmm I'm not so sure about this. While mine is longer form at least the
intent is clear. What about:

    maxpasses =3D (is_q ? 4 : 2) << hp

It's still a little magical IMHO though...

--
Alex Benn=C3=A9e