From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58282) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ej1By-0007lZ-Kx for qemu-devel@nongnu.org; Tue, 06 Feb 2018 06:13:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ej1Bv-00066W-EI for qemu-devel@nongnu.org; Tue, 06 Feb 2018 06:13:38 -0500 Received: from mail-wr0-x243.google.com ([2a00:1450:400c:c0c::243]:46512) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ej1Bv-00066F-84 for qemu-devel@nongnu.org; Tue, 06 Feb 2018 06:13:35 -0500 Received: by mail-wr0-x243.google.com with SMTP id 35so1459001wrb.13 for ; Tue, 06 Feb 2018 03:13:35 -0800 (PST) References: <20180126045742.5487-1-richard.henderson@linaro.org> <20180126045742.5487-19-richard.henderson@linaro.org> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <20180126045742.5487-19-richard.henderson@linaro.org> Date: Tue, 06 Feb 2018 11:13:32 +0000 Message-ID: <87h8quweub.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v11 18/20] target/arm: Use vector infrastructure for aa64 orr/bic immediate List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org Richard Henderson writes: > Reviewed-by: Peter Maydell > Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e > --- > target/arm/translate-a64.c | 28 +++++----------------------- > 1 file changed, 5 insertions(+), 23 deletions(-) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 64a2c2df59..d688a699be 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -6180,7 +6180,6 @@ static void disas_simd_mod_imm(DisasContext *s, uin= t32_t insn) > bool is_neg =3D extract32(insn, 29, 1); > bool is_q =3D extract32(insn, 30, 1); > uint64_t imm =3D 0; > - int i; > > if (o2 !=3D 0 || ((cmode =3D=3D 0xf) && is_neg && !is_q)) { > unallocated_encoding(s); > @@ -6266,29 +6265,12 @@ static void disas_simd_mod_imm(DisasContext *s, u= int32_t insn) > tcg_gen_gvec_dup64i(vec_full_reg_offset(s, rd), is_q ? 16 : 8, > vec_full_reg_size(s), imm); > } else { > - TCGv_i64 tcg_imm =3D tcg_const_i64(imm); > - TCGv_i64 tcg_rd =3D new_tmp_a64(s); > - > - for (i =3D 0; i < 2; i++) { > - int foffs =3D vec_reg_offset(s, rd, i, MO_64); > - > - if (i =3D=3D 1 && !is_q) { > - /* non-quad ops clear high half of vector */ > - tcg_gen_movi_i64(tcg_rd, 0); > - } else { > - tcg_gen_ld_i64(tcg_rd, cpu_env, foffs); > - if (is_neg) { > - /* AND (BIC) */ > - tcg_gen_and_i64(tcg_rd, tcg_rd, tcg_imm); > - } else { > - /* ORR */ > - tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_imm); > - } > - } > - tcg_gen_st_i64(tcg_rd, cpu_env, foffs); > + /* ORR or BIC, with BIC negation to AND handled above. */ > + if (is_neg) { > + gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_andi, MO_64= ); > + } else { > + gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_ori, MO_64); > } > - > - tcg_temp_free_i64(tcg_imm); > } > } -- Alex Benn=C3=A9e