From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40416) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1af12c-0002Jg-RT for qemu-devel@nongnu.org; Sun, 13 Mar 2016 04:06:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1af12Z-0001BW-8H for qemu-devel@nongnu.org; Sun, 13 Mar 2016 04:06:22 -0400 Received: from mail-wm0-x230.google.com ([2a00:1450:400c:c09::230]:36540) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1af12Z-0001BL-0m for qemu-devel@nongnu.org; Sun, 13 Mar 2016 04:06:19 -0400 Received: by mail-wm0-x230.google.com with SMTP id n186so68951811wmn.1 for ; Sun, 13 Mar 2016 00:06:18 -0800 (PST) References: From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: Date: Sun, 13 Mar 2016 08:06:16 +0000 Message-ID: <87h9ga6buv.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] Regarding TB retranslation code. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Venkatesh N Cc: qemu-devel@nongnu.org Venkatesh N writes: > This is regarding TB retranslation code. > > [Qemu-devel] [RFC 00/20] Do away with TB retranslation, Richard Henderson <= > > Though i understood the code to avoid the retranslation, i could not > get picture on how "host" or backend registers are ensured to have the > older contents when the guest PC is restored from > "cpu_restore_state_from_tb" > > For e.g, lets take these two Guest Instruction. > > Instruction 1. Mov r1, [r2]; > Instruction 2. mov [r1], r3 <-------- faulted instruction > > In the above example if r1 is stored in x86 register EAX of the Host > and r3 is stored in EBX of the host. The key thing to realise is the guests register state is not set until the host temporary registers are stored back to the memory representing the guest register state. This does mean the TCG has to ensure the values of guest registers are written back to memory before another potentially faulting instruction can occur. While there are mechanisms we could use to track where the current value of a guest register is currently held we don't do this currently. > > the return from fault ensures that guest PC [EIP ] is recovered. But, > How does tcg ensures that execution of TB from the restored PC ensures > that HOST registers contents have instruction 1 context also. > > Can somebody please share how this is done are there any assumption > when inserting TCG-Opcode INDEX_op_insn_start is done. -- Alex Bennée