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From: Andi Kleen <andi@firstfloor.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: LKML <linux-kernel@vger.kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	x86@kernel.org, Borislav Petkov <bp@alien8.de>,
	Stephane Eranian <eranian@google.com>,
	Harish Chegondi <harish.chegondi@intel.com>,
	Kan Liang <kan.liang@intel.com>,
	Andi Kleen <andi.kleen@intel.com>,
	Jacob Pan <jacob.jun.pan@linux.intel.com>
Subject: Re: [patch V2 11/28] x86/topology: Create logical package id
Date: Mon, 22 Feb 2016 10:54:01 -0800	[thread overview]
Message-ID: <87h9h0pody.fsf@tassilo.jf.intel.com> (raw)
In-Reply-To: <20160222110441.100696947@linutronix.de> (Thomas Gleixner's message of "Mon, 22 Feb 2016 11:06:50 -0000")

Thomas Gleixner <tglx@linutronix.de> writes:


> +
> +	if (c->cpuid_level >= 0x00000001) {
> +		u32 eax, ebx, ecx, edx;
> +
> +		cpuid(0x00000001, &eax, &ebx, &ecx, &edx);

Use cpuid_edx()

> +		/*
> +		 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
> +		 * apicids which are reserved per package. Store the resulting
> +		 * shift value for the package management code.
> +		 */
> +		if (edx & (1U << 28))
> +			c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
> +	}
> +++ b/arch/x86/kernel/cpu/proc.c
> @@ -12,6 +12,7 @@ static void show_cpuinfo_core(struct seq
>  {
>  #ifdef CONFIG_SMP
>  	seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
> +	seq_printf(m, "logical id\t: %d\n", c->logical_proc_id);


I'm not sure it makes sense to export this. What good would it be for
the user?

If it was it would need to be documented somewhere. But I would
just drop it and keep it kernel internal.

FWIW every time something is added to this file it usually breaks
some (dumb) programs.

> +	/*
> +	 * Today neither Intel nor AMD support heterogenous systems. That
> +	 * might change in the future....
> +	 */
> +	ncpus = boot_cpu_data.x86_max_cores * smp_num_siblings;
> +	__max_logical_packages = DIV_ROUND_UP(nr_cpu_ids, ncpus);

FWIW Hypervisors can do nearly everything today.

I assume your code handles it.

Let's hope that the Hypervisors always set up the correct CPUID now
for their sibling configuration. If they don't with this change
some CPUs would be suddenly lost.

Would it be worth to have a kernel option where the maximum can be overriden
in case this happens?


-Andi
-- 
ak@linux.intel.com -- Speaking for myself only

  reply	other threads:[~2016-02-22 18:54 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-22 11:06 [patch V2 00/28] x86/perf/intel/uncore|rapl: Fix error handling and sanitize pmu management Thomas Gleixner
2016-02-22 11:06 ` [patch V2 01/28] x86/perf/intel/uncore: Remove pointless mask check Thomas Gleixner
2016-02-22 11:06 ` [patch V2 02/28] x86/perf/intel/uncore: Simplify error rollback Thomas Gleixner
2016-02-22 11:06 ` [patch V2 03/28] x86/perf/intel/uncore: Fix error handling Thomas Gleixner
2016-02-22 11:06 ` [patch V2 04/28] x86/perf/intel/uncore: Add sanity checks for pci dev package id Thomas Gleixner
2016-02-22 11:06 ` [patch V2 05/28] x86/perf/intel_uncore: Cleanup hardware on exit Thomas Gleixner
2016-02-22 11:06 ` [patch V2 06/28] x86/perf/intel/uncore: Drop pointless hotplug priority Thomas Gleixner
2016-02-22 11:06 ` [patch V2 07/28] x86/perf/intel_uncore: Make code readable Thomas Gleixner
2016-02-22 11:06 ` [patch V2 08/28] x86/perf/uncore: Make uncore_pcibus_to_physid static Thomas Gleixner
2016-02-22 11:06 ` [patch V2 09/28] perf: Allow storage of pmu private data in event Thomas Gleixner
2016-02-22 11:06 ` [patch V2 10/28] x86/perf/intel_uncore: Store box in event->pmu_private Thomas Gleixner
2016-02-22 11:45   ` Peter Zijlstra
2016-02-22 11:58     ` Thomas Gleixner
2016-02-22 11:52   ` Peter Zijlstra
2016-02-22 12:00     ` Thomas Gleixner
2016-02-22 11:06 ` [patch V2 11/28] x86/topology: Create logical package id Thomas Gleixner
2016-02-22 18:54   ` Andi Kleen [this message]
2016-02-22 19:05     ` Thomas Gleixner
2016-02-22 11:06 ` [patch V2 12/28] x86/perf/uncore: Track packages not per cpu data Thomas Gleixner
2016-02-22 11:06 ` [patch V2 13/28] x86/perf/intel_uncore: Clear all hardware state on exit Thomas Gleixner
2016-02-22 11:58   ` Peter Zijlstra
2016-02-22 11:59     ` Thomas Gleixner
2016-02-22 11:06 ` [patch V2 15/28] cpumask: Export cpumask_any_but Thomas Gleixner
2016-02-22 11:06 ` [patch V2 14/28] x86/perf/intel_uncore: Make PCI and MSR uncore independent Thomas Gleixner
2016-02-22 11:06 ` [patch V2 16/28] x86/perf/intel_uncore: Make it modular Thomas Gleixner
2016-02-22 11:06 ` [patch V2 17/28] x86/perf/cqm: Get rid of the silly for_each_cpu lookups Thomas Gleixner
2016-02-22 11:06 ` [patch V2 19/28] x86/perf/intel/rapl: Add proper error handling Thomas Gleixner
2016-02-22 11:06 ` [patch V2 18/28] x86/perf/intel_rapl: Make Knights Landings support functional Thomas Gleixner
2016-02-22 20:38   ` Borislav Petkov
2016-02-22 11:06 ` [patch V2 20/28] x86/perf/intel/rapl: Sanitize the quirk handling Thomas Gleixner
2016-02-22 11:06 ` [patch V2 21/28] x86/perf/intel/rapl: Calculate timing once Thomas Gleixner
2016-02-22 11:06 ` [patch V2 23/28] x86/perf/intel/rapl: Refactor code some more Thomas Gleixner
2016-02-22 11:06 ` [patch V2 22/28] x86/perf/intel/rapl: Cleanup the printk output Thomas Gleixner
2016-02-22 18:44   ` Andi Kleen
2016-02-22 18:58     ` Thomas Gleixner
2016-02-22 11:07 ` [patch V2 24/28] x86/perf/intel/rapl: Make pmu lock raw Thomas Gleixner
2016-02-22 11:07 ` [patch V2 25/28] x86/perf/intel/rapl: Utilize event->pmu_private Thomas Gleixner
2016-02-22 11:07 ` [patch V2 26/28] x86/perf/intel/rapl: Convert it to a per package facility Thomas Gleixner
2016-02-22 12:08   ` Peter Zijlstra
2016-02-22 15:52     ` Thomas Gleixner
2016-02-22 16:04       ` Peter Zijlstra
2016-02-22 11:07 ` [patch V2 28/28] x86/perf/intel/rapl: Make it modular Thomas Gleixner
2016-02-22 18:40   ` Andi Kleen
2016-02-22 19:11     ` Thomas Gleixner
2016-02-22 11:07 ` [patch V2 27/28] perf: Export perf_event_sysfs_show Thomas Gleixner
2016-02-22 12:09   ` Peter Zijlstra
2016-02-22 18:55 ` [patch V2 00/28] x86/perf/intel/uncore|rapl: Fix error handling and sanitize pmu management Andi Kleen

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