From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40096) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zross-0007fx-EN for qemu-devel@nongnu.org; Thu, 29 Oct 2015 11:12:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zrosp-00046g-Mj for qemu-devel@nongnu.org; Thu, 29 Oct 2015 11:12:58 -0400 Received: from mail-wi0-x22c.google.com ([2a00:1450:400c:c05::22c]:34601) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zrosp-00046Z-H8 for qemu-devel@nongnu.org; Thu, 29 Oct 2015 11:12:55 -0400 Received: by wikq8 with SMTP id q8so287584510wik.1 for ; Thu, 29 Oct 2015 08:12:55 -0700 (PDT) References: <1445883178-576-1-git-send-email-peter.maydell@linaro.org> <1445883178-576-2-git-send-email-peter.maydell@linaro.org> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1445883178-576-2-git-send-email-peter.maydell@linaro.org> Date: Thu, 29 Oct 2015 15:12:53 +0000 Message-ID: <87h9l9wvwq.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH for-2.5 1/2] target-arm: Bring AArch64 debug CPU display of PSTATE into line with AArch32 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: "Edgar E. Iglesias" , qemu-devel@nongnu.org, patches@linaro.org Peter Maydell writes: > The AArch64 debug CPU display of PSTATE as "PSTATE=200003c5 (flags --C-)" > on the end of the same line as the last of the general purpose registers > is unnecessarily different from the AArch32 display of PSR as > "PSR=200001d3 --C- A svc32" on its own line. Update the AArch64 > code to put PSTATE in its own line and in the same format, including > printing the exception level (mode). > > Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée > --- > target-arm/translate-a64.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c > index 19f9d8d..ccefa7b 100644 > --- a/target-arm/translate-a64.c > +++ b/target-arm/translate-a64.c > @@ -126,6 +126,7 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, > CPUARMState *env = &cpu->env; > uint32_t psr = pstate_read(env); > int i; > + int el = arm_current_el(env); > > cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n", > env->pc, env->xregs[31]); > @@ -137,13 +138,14 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, > cpu_fprintf(f, " "); > } > } > - cpu_fprintf(f, "PSTATE=%08x (flags %c%c%c%c)\n", > + cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c EL%d%c\n", > psr, > psr & PSTATE_N ? 'N' : '-', > psr & PSTATE_Z ? 'Z' : '-', > psr & PSTATE_C ? 'C' : '-', > - psr & PSTATE_V ? 'V' : '-'); > - cpu_fprintf(f, "\n"); > + psr & PSTATE_V ? 'V' : '-', > + el, > + psr & PSTATE_SP ? 'h' : 't'); > > if (flags & CPU_DUMP_FPU) { > int numvfpregs = 32; -- Alex Bennée