From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49613) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wrm1i-0006kq-Fj for qemu-devel@nongnu.org; Tue, 03 Jun 2014 06:33:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wrm1d-0004Cl-42 for qemu-devel@nongnu.org; Tue, 03 Jun 2014 06:33:06 -0400 Received: from static.88-198-71-155.clients.your-server.de ([88.198.71.155]:46263 helo=socrates.bennee.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wrm1c-0004CS-Tk for qemu-devel@nongnu.org; Tue, 03 Jun 2014 06:33:01 -0400 References: <1401434911-26992-1-git-send-email-edgar.iglesias@gmail.com> <1401434911-26992-11-git-send-email-edgar.iglesias@gmail.com> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1401434911-26992-11-git-send-email-edgar.iglesias@gmail.com> Date: Tue, 03 Jun 2014 11:32:59 +0100 Message-ID: <87ha42s2p0.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v1 10/16] target-arm: Break out exception masking to a separate func List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Edgar E. Iglesias" Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, rob.herring@linaro.org, aggelerf@ethz.ch, qemu-devel@nongnu.org, agraf@suse.de, blauwirbel@gmail.com, john.williams@xilinx.com, greg.bellows@linaro.org, pbonzini@redhat.com, christoffer.dall@linaro.org, rth@twiddle.net Edgar E. Iglesias writes: > From: "Edgar E. Iglesias" > > Signed-off-by: Edgar E. Iglesias > --- > cpu-exec.c | 5 ++--- > target-arm/cpu.h | 16 ++++++++++++++++ > 2 files changed, 18 insertions(+), 3 deletions(-) > > diff --git a/cpu-exec.c b/cpu-exec.c > index 38e5f02..a579ffc 100644 > --- a/cpu-exec.c > +++ b/cpu-exec.c > @@ -478,7 +478,7 @@ int cpu_exec(CPUArchState *env) > } > #elif defined(TARGET_ARM) > if (interrupt_request & CPU_INTERRUPT_FIQ > - && !(env->daif & PSTATE_F)) { > + && arm_excp_unmasked(cpu, EXCP_FIQ)) { > cpu->exception_index = EXCP_FIQ; > cc->do_interrupt(cpu); > next_tb = 0; > @@ -493,8 +493,7 @@ int cpu_exec(CPUArchState *env) > We avoid this by disabling interrupts when > pc contains a magic address. */ > if (interrupt_request & CPU_INTERRUPT_HARD > - && ((IS_M(env) && env->regs[15] < 0xfffffff0) > - || !(env->daif & PSTATE_I))) { > + && arm_excp_unmasked(cpu, EXCP_IRQ)) { > cpu->exception_index = EXCP_IRQ; > cc->do_interrupt(cpu); > next_tb = 0; > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 5c74adc..9eddcc1 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -1130,6 +1130,22 @@ bool write_cpustate_to_list(ARMCPU *cpu); > # define TARGET_VIRT_ADDR_SPACE_BITS 32 > #endif > > +static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) > +{ > + CPUARMState *env = cs->env_ptr; > + > + switch (excp_idx) { > + case EXCP_FIQ: > + return !(env->daif & PSTATE_F); > + case EXCP_IRQ: > + return ((IS_M(env) && env->regs[15] < 0xfffffff0) > + || !(env->daif & PSTATE_I)); > + default: > + assert(0); g_assert_not_reached() is clearer about the intent here. > + break; > + } > +} > + > static inline CPUARMState *cpu_init(const char *cpu_model) > { > ARMCPU *cpu = cpu_arm_init(cpu_model); -- Alex Bennée