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Tue, 13 Oct 2026 01:42:59 -0700 (PDT) Received: from draig.lan ([185.124.0.156]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48de0ab5262sm3937232f8f.22.2026.10.13.01.42.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2026 01:42:58 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 4098C5F8E5; Tue, 13 Oct 2026 09:42:57 +0100 (BST) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: =?utf-8?Q?Marc-Andr=C3=A9?= Lureau Cc: qemu-devel@nongnu.org, "Dr. David Alan Gilbert" , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Zhao Liu , Peter Maydell , Chinmay Rath , Nicholas Piggin , Glenn Miles , Harsh Prateek Bora , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Max Filippov , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, Paolo Bonzini , Laurent Vivier , Mark Cave-Ayland , Artyom Tarasenko , Helge Deller , Pierrick Bouvier , Warner Losh , Kyle Evans Subject: Re: [PATCH v2 04/10] gdbstub: add gdb_register_internal_coprocessor() In-Reply-To: <20261013-query-reg-v2-4-6f95a2e139a9@redhat.com> (=?utf-8?Q?=22Marc-Andr=C3=A9?= Lureau"'s message of "Tue, 13 Oct 2026 00:34:07 +0400") References: <20261013-query-reg-v2-0-6f95a2e139a9@redhat.com> <20261013-query-reg-v2-4-6f95a2e139a9@redhat.com> User-Agent: mu4e 1.14.4-pre6; emacs 30.1 Date: Tue, 13 Oct 2026 09:42:57 +0100 Message-ID: <87ik36gfe6.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Marc-Andr=C3=A9 Lureau writes: > Add support for registering coprocessor features that are only visible > to QEMU's internal APIs (HMP monitor $register expressions, plugins) but > hidden from GDB's target description XML. > > When a feature is registered as internal: > - It is excluded from the target.xml sent to GDB > - Its XML is not served via qXfer:features:read > - 'p'/'P' packets for internal register numbers return E14 > > This is useful for exposing system registers to the HMP monitor without > affecting GDB's register namespace. Exposing aliases or synthetic > registers through GDB's target description can cause problems: name > collisions with GDB's pseudo-registers, independent register caching, > and missing DWARF unwind rules. Hmm are they *that* useful for HMP then? The front-ends do limit what they export to gdb (see for example ARM_CP_NO_GDB) generally because reading them causes side-effects. Those restrictions are also a reason to limit them from the HMP interface. > > Internal features must be registered after all GDB-visible features to > keep remote register numbering consistent. This ordering is enforced > with an assertion. > > Signed-off-by: Marc-Andr=C3=A9 Lureau > --- > gdbstub/gdbstub.c | 71 ++++++++++++++++++++++++++++++++++++++++++++= ------ > include/exec/gdbstub.h | 21 +++++++++++++++ > 2 files changed, 84 insertions(+), 8 deletions(-) > > diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c > index 912e31b66744..ac0f76d62333 100644 > --- a/gdbstub/gdbstub.c > +++ b/gdbstub/gdbstub.c > @@ -54,6 +54,7 @@ typedef struct GDBRegisterState { > gdb_get_reg_cb get_reg; > gdb_set_reg_cb set_reg; > const GDBFeature *feature; > + bool internal; /* hidden from GDB, accessible via API/monitor */ > } GDBRegisterState; >=20=20 > GDBState gdbserver_state; > @@ -385,6 +386,11 @@ static const char *get_feature_xml(const char *p, co= nst char **newp, > } > for (guint i =3D 0; i < cpu->gdb_regs->len; i++) { > r =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); > + /* The core target.xml feature must never be internal. */ > + g_assert(i > 0 || !r->internal); > + if (r->internal) { > + continue; > + } > g_ptr_array_add( > xml, > g_markup_printf_escaped("= ", > @@ -400,6 +406,9 @@ static const char *get_feature_xml(const char *p, con= st char **newp, > /* Is it one of the features? */ > for (guint i =3D 0; i < cpu->gdb_regs->len; i++) { > r =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); > + if (r->internal) { > + continue; > + } > if (strncmp(p, r->feature->xmlname, len) =3D=3D 0) { > return r->feature->xml; > } > @@ -563,13 +572,14 @@ int gdb_write_register(CPUState *cpu, uint8_t *mem_= buf, int reg) >=20=20 > static void gdb_register_feature(CPUState *cpu, int base_reg, > gdb_get_reg_cb get_reg, gdb_set_reg_cb = set_reg, > - const GDBFeature *feature) > + const GDBFeature *feature, bool interna= l) > { > GDBRegisterState s =3D { > .base_reg =3D base_reg, > .get_reg =3D get_reg, > .set_reg =3D set_reg, > - .feature =3D feature > + .feature =3D feature, > + .internal =3D internal > }; >=20=20 > trace_gdbxml_register_feature(feature->name, feature->xmlname, > @@ -605,7 +615,7 @@ void gdb_init_cpu(CPUState *cpu) > assert(feature->base_reg =3D=3D 0); > gdb_register_feature(cpu, 0, > cc->gdb_read_register, cc->gdb_write_regist= er, > - feature); > + feature, false); > cpu->gdb_next_base_reg =3D cpu->gdb_num_g_regs =3D feature->num_= regs; > } else { > cpu->gdb_next_base_reg =3D cpu->gdb_num_g_regs =3D cc->gdb_num_c= ore_regs; > @@ -616,20 +626,26 @@ void gdb_init_cpu(CPUState *cpu) > cc->gdb_num_core_regs); > } >=20=20 > -void gdb_register_coprocessor(CPUState *cpu, > - gdb_get_reg_cb get_reg, gdb_set_reg_cb set= _reg, > - const GDBFeature *feature) > +static void do_gdb_register_coprocessor(CPUState *cpu, > + gdb_get_reg_cb get_reg, > + gdb_set_reg_cb set_reg, > + const GDBFeature *feature, > + bool internal) > { > GDBRegisterState *s; > guint i; > int base_reg =3D cpu->gdb_next_base_reg; >=20=20 > for (i =3D 0; i < cpu->gdb_regs->len; i++) { > - /* Check for duplicates. */ > s =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); > + /* Check for duplicates. */ > if (s->feature =3D=3D feature) { > return; > } > + /* GDB-visible features must not follow internal ones. */ > + if (!internal) { > + g_assert(!s->internal); > + } > } >=20=20 > if (base_reg < feature->base_reg) { > @@ -637,12 +653,27 @@ void gdb_register_coprocessor(CPUState *cpu, > feature->base_reg); > base_reg =3D feature->base_reg; > } > - gdb_register_feature(cpu, base_reg, get_reg, set_reg, feature); > + gdb_register_feature(cpu, base_reg, get_reg, set_reg, feature, inter= nal); >=20=20 > /* Add to end of list. */ > cpu->gdb_next_base_reg =3D base_reg + feature->num_regs; > } >=20=20 > +void gdb_register_coprocessor(CPUState *cpu, > + gdb_get_reg_cb get_reg, gdb_set_reg_cb set= _reg, > + const GDBFeature *feature) > +{ > + do_gdb_register_coprocessor(cpu, get_reg, set_reg, feature, false); > +} > + > +void gdb_register_internal_coprocessor(CPUState *cpu, > + gdb_get_reg_cb get_reg, > + gdb_set_reg_cb set_reg, > + const GDBFeature *feature) > +{ > + do_gdb_register_coprocessor(cpu, get_reg, set_reg, feature, true); > +} > + > void gdb_unregister_coprocessor_all(CPUState *cpu) > { > /* > @@ -1223,6 +1254,18 @@ static void handle_remove_bp(GArray *params, void = *user_ctx) > * the remote gdb to fallback to older methods. > */ >=20=20 > +static bool gdb_register_is_internal(CPUState *cpu, int reg) > +{ > + for (guint i =3D 0; i < cpu->gdb_regs->len; i++) { > + GDBRegisterState *r =3D &g_array_index(cpu->gdb_regs, GDBRegiste= rState, i); > + > + if (r->base_reg <=3D reg && reg < r->base_reg + r->feature->num_= regs) { > + return r->internal; > + } > + } > + return false; > +} > + > static void handle_set_reg(GArray *params, void *user_ctx) > { > int reg_size; > @@ -1232,6 +1275,12 @@ static void handle_set_reg(GArray *params, void *u= ser_ctx) > return; > } >=20=20 > + if (gdb_register_is_internal(gdbserver_state.g_cpu, > + gdb_get_cmd_param(params, 0)->val_ull))= { > + gdb_put_packet("E14"); > + return; > + } > + > reg_size =3D strlen(gdb_get_cmd_param(params, 1)->data) / 2; > gdb_hextomem(gdbserver_state.mem_buf, gdb_get_cmd_param(params, 1)->= data, reg_size); > gdb_write_register(gdbserver_state.g_cpu, gdbserver_state.mem_buf->d= ata, > @@ -1248,6 +1297,12 @@ static void handle_get_reg(GArray *params, void *u= ser_ctx) > return; > } >=20=20 > + if (gdb_register_is_internal(gdbserver_state.g_cpu, > + gdb_get_cmd_param(params, 0)->val_ull))= { > + gdb_put_packet("E14"); > + return; > + } > + > reg_size =3D gdb_read_register(gdbserver_state.g_cpu, > gdbserver_state.mem_buf, > gdb_get_cmd_param(params, 0)->val_ull); > diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h > index 75eb4d9c365e..1bc778324758 100644 > --- a/include/exec/gdbstub.h > +++ b/include/exec/gdbstub.h > @@ -40,6 +40,27 @@ void gdb_register_coprocessor(CPUState *cpu, > gdb_get_reg_cb get_reg, gdb_set_reg_cb set= _reg, > const GDBFeature *feature); >=20=20 > +/** > + * gdb_register_internal_coprocessor() - register internal registers > + * > + * Like gdb_register_coprocessor(), but the feature is NOT exposed to > + * GDB via the target description XML. The registers are only > + * accessible through QEMU's internal APIs (HMP monitor ``$register`` > + * expressions via gdb_get_register_list()). > + * > + * Internal features must be registered after all GDB-visible features > + * to avoid register numbering mismatches with GDB. > + * > + * @cpu - the CPU associated with registers > + * @get_reg - get function > + * @set_reg - set function > + * @feature - the GDBFeature describing the registers > + */ > +void gdb_register_internal_coprocessor(CPUState *cpu, > + gdb_get_reg_cb get_reg, > + gdb_set_reg_cb set_reg, > + const GDBFeature *feature); > + > /** > * gdb_unregister_coprocessor_all() - unregisters supplemental set of re= gisters > * @cpu - the CPU associated with registers --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro