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Tsirkin" , Peter Xu , David Hildenbrand , =?utf-8?Q?Cl?= =?utf-8?Q?=C3=A9ment?= Mathieu--Drif , Paolo Bonzini , Daniel Henrique Barboza , Peter Maydell , Zhao Liu , "Edgar E. Iglesias" , =?utf-8?Q?Cl=C3=A9ment?= Chigot , Frederic Konrad Subject: Re: [PATCH] exec: Add RISC-V WorldGuard WID field to MemTxAttrs In-Reply-To: <08c5f243-5aaa-4fe2-bc71-6a3fd9a1914e@linaro.org> ("Philippe =?utf-8?Q?Mathieu-Daud=C3=A9=22's?= message of "Wed, 18 Mar 2026 07:42:31 +0100") References: <20260209115846.2276651-1-jim.shu@sifive.com> <7be3b4f7-7516-40ab-8a95-b3b4a2aea095@linaro.org> <08c5f243-5aaa-4fe2-bc71-6a3fd9a1914e@linaro.org> User-Agent: mu4e 1.14.3-pre1; emacs 30.1 Date: Fri, 17 Jul 2026 11:08:28 +0100 Message-ID: <87ik6e2ajn.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Philippe Mathieu-Daud=C3=A9 writes: > On 18/3/26 05:40, Jim Shu wrote: >> On Tue, Feb 10, 2026 at 8:25=E2=80=AFAM Richard Henderson >> wrote: >> ... >>> Hmm. This really overlaps the secure and space fields from arm, and po= ssibly some of the >>> others as well (e.g. user, requester_id, pid). >>> >>> I don't really have a good suggestion for that right now, but it would = be nice to not keep >>> expanding the count of these sorts of fields that somehow specify the o= riginator, but >>> clearly cannot overlap. >>> >>> I'm reasonably sure we've had this discussion before, but nothing has c= ome of it. >>> >>> Time to paint the bikeshed again? > > Last discussion IIRC: > https://lore.kernel.org/qemu-devel/CAFEAcA8vKNkfKgp_Yymo9NA1=3DE2XJYXAMTg= O3z6q6DHgqkAwRw@mail.gmail.com/ > > (see also a suggestion in > https://lore.kernel.org/qemu-devel/Z4+P3eHXqcU4Dqdx@intel.com/) Also somewhat related: Message-Id: <20221111182535.64844-1-alex.bennee@linaro.org> Date: Fri, 11 Nov 2022 18:25:15 +0000 Subject: [PATCH for 8.0 v5 00/20] use MemTxAttrs to avoid current_cpu in = hw/ Another case that was mentioned in a Core Collective meeting was handling MMIO devices with IOMMUs (currently requester_id is tied to PCI). I guess the WorldGuard WID field is a similar thing. > >>> >> I can union the 'secure' and 'world_id' fields, as they are not used >> together. >> However, I have no idea about the 'space' fields. >> I have seen CPUTLBEntryFull has the extra union to support >> ARM-specific members. >> Another idea is that also adding the extra union to MemTxAttrs to >> place the RISC-V worid_id. >> We can use this extra union to as SoC-specific signals in the bus, >> like AXI AxUSER signal. >> Do you think it is suitable? >> Thanks, >> Jim --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro