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Mon, 09 Jun 2025 08:20:50 -0700 (PDT) Received: from draig.lan ([185.126.160.19]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ade1dc7c765sm571607466b.178.2025.06.09.08.20.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jun 2025 08:20:49 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 849BE5F8A4; Mon, 09 Jun 2025 16:20:48 +0100 (BST) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Rowan Hart Cc: Julian Ganz , Marcel Apfelbaum , Mahmoud Mandour , Richard Henderson , Eduardo Habkost , Yanan Wang , Pierrick Bouvier , Paolo Bonzini , Zhao Liu , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Alexandre Iooss , qemu-devel@nongnu.org Subject: Re: [PATCH v9 3/9] plugins: Add enforcement of QEMU_PLUGIN_CB flags in register R/W callbacks In-Reply-To: (Rowan Hart's message of "Mon, 9 Jun 2025 07:55:18 -0700") References: <20250608230819.3382527-1-rowanbhart@gmail.com> <20250608230819.3382527-4-rowanbhart@gmail.com> <20250609135636.22368-1-neither@nut.email> User-Agent: mu4e 1.12.11; emacs 30.1 Date: Mon, 09 Jun 2025 16:20:48 +0100 Message-ID: <87ikl5kkkv.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Rowan Hart writes: > However, it should be safe at least for a subset of those callbacks and > > I believe there are very valid use-cases for allowing such usage. For > example, we are currently working on a plugin API exposing traps. In > those callbacks, users may want to peek at some registers such as > "ecause" and "tval" (on RISC-V). We certainly will want to do so for the > use-case we are pushing that API for. > > We could add a QEMU_PLUGIN_CB flag parameter to the respective > registration functions. But since they are not run from translated > blocks but _outside_ that context, I feel they would just clutter the > API without introducing any real benefit. That is, if there is no valid > safety or correctness concern that I'm not aware of. > > This makes sense, I think we could just set QEMU_PLUGIN_CB_RW_REGS for th= ese callbacks if they're always called in a state > where the stated requirements are met (I think they are). This would avoi= d breaking compatibility while maintaining the > functionality. Same as you, I looked around and it seems like the vcpu_(i= nit|idle|exit) locations are definitely okay, I'll check > into the tb_trans callback, I'm not entirely sure about it. It should be OK here too. The CB_RW_REGS flags are only needed for callback from within the translated code - much like their cousins the TCG helpers. All register state should rectified if we are no longer running translated code - indeed currently it is rectified by the time we leave the translated block and before we start the next one. There are some edge cases when we handle exceptions but we should have fixed up any register state before we longjmp back to the start of the run loop. --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro