Re: [PATCH v2 1/2] drm/i915/cx0: Pass crtc_state to intel_c20_compute_hdmi_tmds_pll()

[Jani Nikula <jani.nikula@intel.com>]

On Wed, 23 Oct 2024, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> The variable crtc_state already contains everything that
> intel_c20_compute_hdmi_tmds_pll() needs. Simplify the function's
> signature by passing that struct instead of separate variables.
>
> Suggested-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index f73d576fd99e..996c3c6edd41 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2142,8 +2142,9 @@ static void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
>  			    i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
>  }
>  
> -static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_state *pll_state)
> +static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state)
>  {
> +	struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20;
>  	u64 datarate;
>  	u64 mpll_tx_clk_div;
>  	u64 vco_freq_shift;
> @@ -2155,10 +2156,10 @@ static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_
>  	u8  mpllb_ana_freq_vco;
>  	u8  mpll_div_multiplier;
>  
> -	if (pixel_clock < 25175 || pixel_clock > 600000)
> +	if (crtc_state->port_clock < 25175 || crtc_state->port_clock > 600000)
>  		return -EINVAL;
>  
> -	datarate = ((u64)pixel_clock * 1000) * 10;
> +	datarate = ((u64)crtc_state->port_clock * 1000) * 10;
>  	mpll_tx_clk_div = ilog2(div64_u64((u64)CLOCK_9999MHZ, (u64)datarate));
>  	vco_freq_shift = ilog2(div64_u64((u64)CLOCK_4999MHZ * (u64)256, (u64)datarate));
>  	vco_freq = (datarate << vco_freq_shift) >> 8;
> @@ -2180,7 +2181,7 @@ static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_
>  	else
>  		mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_0;
>  
> -	pll_state->clock	= pixel_clock;
> +	pll_state->clock	= crtc_state->port_clock;
>  	pll_state->tx[0]	= 0xbe88;
>  	pll_state->tx[1]	= 0x9800;
>  	pll_state->tx[2]	= 0x0000;
> @@ -2266,8 +2267,7 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
>  
>  	/* try computed C20 HDMI tables before using consolidated tables */
>  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> -		if (intel_c20_compute_hdmi_tmds_pll(crtc_state->port_clock,
> -						    &crtc_state->dpll_hw_state.cx0pll.c20) == 0)
> +		if (intel_c20_compute_hdmi_tmds_pll(crtc_state) == 0)
>  			return 0;
>  	}

-- 
Jani Nikula, Intel