From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AFFC4C4167B for ; Wed, 1 Nov 2023 15:23:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 86D2C10E71F; Wed, 1 Nov 2023 15:23:29 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id D429010E71F for ; Wed, 1 Nov 2023 15:23:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698852207; x=1730388207; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=YL8pxFAagmoGsy4q9PId+dRqcMRjg/Ec3Mqc7c76mkU=; b=giDlxSUNuvNM72PtlPRJZdh/9bMhBzSTle0vPojCeCOB89/H82M83tXk +Q/ZrJFrvkhhtRa2brXqbwfeTsCVesgOjB5XhxB0EJRJariJEFOsdq7QX WIgdKmE+23PlkRYFAaOqSsn22nYgIIeeV6eDXJPDxrw7h11PQrCgftYgM uC0j4TS7UV5VqC0qmXiSIvmb4KqKIslcg9gmT5MzQ9VHt9g5jJxD1UVPH t0sH7cBI1ozZBO30Gw1dMnWbMfy8XanhDIiByPQgPJaxtoonvr8Af9HSw brZsbEZWz9allN9VGOOBYAZH9PglNNQoEuhdp9cpCdsMWZwX5+b9+VLwY w==; X-IronPort-AV: E=McAfee;i="6600,9927,10881"; a="391380491" X-IronPort-AV: E=Sophos;i="6.03,268,1694761200"; d="scan'208";a="391380491" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2023 08:23:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,268,1694761200"; d="scan'208";a="9069956" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.251.29.51]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2023 08:23:15 -0700 Date: Wed, 01 Nov 2023 08:23:15 -0700 Message-ID: <87il6la464.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Badal Nilawar In-Reply-To: <20231101151756.1617408-1-badal.nilawar@intel.com> References: <20231101151756.1617408-1-badal.nilawar@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-xe] [PATCH] drm/xe/mtl: Use 16.67 Mhz freq scale factor to get rpX X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-xe@lists.freedesktop.org Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Wed, 01 Nov 2023 08:17:56 -0700, Badal Nilawar wrote: > Hi Badal, > For mtl and above 16.67 Mhz is the scale factor to calculate > rpX frequencies. > > Signed-off-by: Badal Nilawar > --- > drivers/gpu/drm/xe/xe_guc_pc.c | 25 ++++++++++++++----------- > 1 file changed, 14 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c > index 74247e0d3674..90e3e1b56c27 100644 > --- a/drivers/gpu/drm/xe/xe_guc_pc.c > +++ b/drivers/gpu/drm/xe/xe_guc_pc.c > @@ -306,14 +306,15 @@ static int pc_set_max_freq(struct xe_guc_pc *pc, u32 freq) > static void mtl_update_rpe_value(struct xe_guc_pc *pc) > { > struct xe_gt *gt = pc_to_gt(pc); > - u32 reg; > + u32 freq; > > if (xe_gt_is_media_type(gt)) > - reg = xe_mmio_read32(gt, MTL_MPE_FREQUENCY); > + freq = xe_mmio_read32(gt, MTL_MPE_FREQUENCY); > else > - reg = xe_mmio_read32(gt, MTL_GT_RPE_FREQUENCY); > + freq = xe_mmio_read32(gt, MTL_GT_RPE_FREQUENCY); Generally I think we should avoid making these kind of variable name changes, if only to keep the patch small and reduce the review effort. In this case, isn't 'reg' more appropriate anyway? If we retained reg this would be a single line change in this function. > > - pc->rpe_freq = REG_FIELD_GET(MTL_RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER; > + freq = REG_FIELD_GET(MTL_RPE_MASK, freq); > + pc->rpe_freq = decode_freq(freq); > } > > static void tgl_update_rpe_value(struct xe_guc_pc *pc) > @@ -645,18 +646,20 @@ static const struct attribute *pc_attrs[] = { > static void mtl_init_fused_rp_values(struct xe_guc_pc *pc) > { > struct xe_gt *gt = pc_to_gt(pc); > - u32 reg; > + u32 freq; > > xe_device_assert_mem_access(pc_to_xe(pc)); > > if (xe_gt_is_media_type(gt)) > - reg = xe_mmio_read32(gt, MTL_MEDIAP_STATE_CAP); > + freq = xe_mmio_read32(gt, MTL_MEDIAP_STATE_CAP); > else > - reg = xe_mmio_read32(gt, MTL_RP_STATE_CAP); > - pc->rp0_freq = REG_FIELD_GET(MTL_RP0_CAP_MASK, reg) * > - GT_FREQUENCY_MULTIPLIER; > - pc->rpn_freq = REG_FIELD_GET(MTL_RPN_CAP_MASK, reg) * > - GT_FREQUENCY_MULTIPLIER; > + freq = xe_mmio_read32(gt, MTL_RP_STATE_CAP); > + > + freq = REG_FIELD_GET(MTL_RP0_CAP_MASK, freq); > + pc->rp0_freq = decode_freq(freq); > + > + freq = REG_FIELD_GET(MTL_RPN_CAP_MASK, freq); > + pc->rpn_freq = decode_freq(freq); Similar comments here too. > } > > static void tgl_init_fused_rp_values(struct xe_guc_pc *pc) > -- > 2.25.1 > Thanks. -- Ashutosh