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From: Marc Zyngier <maz@kernel.org>
To: Joey Gouly <joey.gouly@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, nd@arm.com,
	alexandru.elisei@arm.com, catalin.marinas@arm.com,
	corbet@lwn.net, james.morse@arm.com, reijiw@google.com,
	suzuki.poulose@arm.com, will@kernel.org
Subject: Re: [PATCH v2 2/3] arm64: add ID_AA64ISAR2_EL1 sys register
Date: Tue, 07 Dec 2021 14:49:02 +0000	[thread overview]
Message-ID: <87ilw01ndt.wl-maz@kernel.org> (raw)
In-Reply-To: <20211207143121.GA50552@e124191.cambridge.arm.com>

On Tue, 07 Dec 2021 14:31:21 +0000,
Joey Gouly <joey.gouly@arm.com> wrote:
> 
> Hi Marc,
> 
> On Tue, Dec 07, 2021 at 12:54:32PM +0000, Marc Zyngier wrote:
> > Hi Joey,
> > 
> > On Tue, 07 Dec 2021 12:42:25 +0000,
> 
> [...]
> 
> > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> > > index adcab9009f9d..5393a00340f5 100644
> > > --- a/arch/arm64/include/asm/sysreg.h
> > > +++ b/arch/arm64/include/asm/sysreg.h
> > > @@ -182,6 +182,7 @@
> > >  
> > >  #define SYS_ID_AA64ISAR0_EL1		sys_reg(3, 0, 0, 6, 0)
> > >  #define SYS_ID_AA64ISAR1_EL1		sys_reg(3, 0, 0, 6, 1)
> > > +#define SYS_ID_AA64ISAR2_EL1		sys_reg(3, 0, 0, 6, 2)
> > >  
> > >  #define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)
> > >  #define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
> > > @@ -771,6 +772,15 @@
> > >  #define ID_AA64ISAR1_GPI_NI			0x0
> > >  #define ID_AA64ISAR1_GPI_IMP_DEF		0x1
> > >  
> > > +/* id_aa64isar2 */
> > > +#define ID_AA64ISAR2_RPRES_SHIFT	4
> > > +#define ID_AA64ISAR2_WFXT_SHIFT		0
> > > +
> > > +#define ID_AA64ISAR2_RPRES_8BIT		0x0
> > > +#define ID_AA64ISAR2_RPRES_12BIT	0x1
> > > +#define ID_AA64ISAR2_WFXT_NI		0x0
> > > +#define ID_AA64ISAR2_WFXT_SUPPORTED	0x2
> > 
> > Maybe I wasn't clear in my earlier comment: you need to enumerate all
> > the architecturally valid values:
> > 
> > #define ID_AA64ISAR2_WFXT_NI		0x0
> > #define ID_AA64ISAR2_WFXT_V1		0x1
> > #define ID_AA64ISAR2_WFXT_V2		0x2
> > 
> > where WFXT_V1 represent the original FEAT_WFxT, and WFXT_V2 the new,
> > more usable FEAT_WFxT2. Even if the original FEAT_WFxT is deprecated,
> > it still exists, and is still the only mandatory option for v8.7.
> 
> The 0b001 behaviour has been removed from the architecture and is
> now listed as reserved, but this has not made it's way into an ARM
> ARM. The only permitted values are 0b000 and 0b0001 (mandatory in
> v8.7)

0b0010, right?

> 
> This can be seen from the documentation here:
>   https://developer.arm.com/documentation/ddi0601/2021-09/AArch64-Registers/ID-AA64ISAR2-EL1--AArch64-Instruction-Set-Attribute-Register-2?lang=en

Yay for retrospective changes to the architecture! :D I guess that
nobody dared building the broken version, so it's all good. Maybe add
a small comment to that effect, so that people looking at outdated
material don't get confused?

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

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  reply	other threads:[~2021-12-07 15:12 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-07 12:42 [PATCH v2 0/3] arm64: Add two HWCAPs for Arm v8.7 FP behaviour Joey Gouly
2021-12-07 12:42 ` [PATCH v2 1/3] arm64: cpufeature: add HWCAP for FEAT_AFP Joey Gouly
2021-12-07 12:42 ` [PATCH v2 2/3] arm64: add ID_AA64ISAR2_EL1 sys register Joey Gouly
2021-12-07 12:54   ` Marc Zyngier
2021-12-07 14:31     ` Joey Gouly
2021-12-07 14:49       ` Marc Zyngier [this message]
2021-12-07 15:38         ` Joey Gouly
2021-12-07 12:42 ` [PATCH v2 3/3] arm64: cpufeature: add HWCAP for FEAT_RPRES Joey Gouly

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