From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33FAEC47089 for ; Wed, 26 May 2021 14:27:07 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EC00561028 for ; Wed, 26 May 2021 14:27:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EC00561028 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 81DB66ED23; Wed, 26 May 2021 14:27:06 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id C139E6ED23 for ; Wed, 26 May 2021 14:27:05 +0000 (UTC) IronPort-SDR: OPK4DCN4MnKdyAby0hB1OSd8tYnL6B9RHOYN5m5DRg3nExupjItDR7+SaHSVSnCG0gDP6dbrcr OP6gaHBZiKow== X-IronPort-AV: E=McAfee;i="6200,9189,9996"; a="288057519" X-IronPort-AV: E=Sophos;i="5.82,331,1613462400"; d="scan'208";a="288057519" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2021 07:27:03 -0700 IronPort-SDR: vCwU3PkB+Jc3FCETTs4lOxPgqZZgNSquiRa5wdPzspVCB0DIOcZNcSRto3oZWda+O2/TDdV/Ul eatq4eNa8KlA== X-IronPort-AV: E=Sophos;i="5.82,331,1613462400"; d="scan'208";a="443062472" Received: from astiegle-mobl.ger.corp.intel.com (HELO localhost) ([10.252.54.167]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2021 07:27:00 -0700 From: Jani Nikula To: Bhanuprakash Modem , intel-gfx@lists.freedesktop.org, nischal.varide@intel.com, uma.shankar@intel.com, anshuman.gupta@intel.com In-Reply-To: <20210526181728.14817-3-bhanuprakash.modem@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20210526181728.14817-1-bhanuprakash.modem@intel.com> <20210526181728.14817-3-bhanuprakash.modem@intel.com> Date: Wed, 26 May 2021 17:26:56 +0300 Message-ID: <87im35bmfj.fsf@intel.com> MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/display/debug: Expose Dither status via debugfs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, 26 May 2021, Bhanuprakash Modem wrote: > It's useful to know the dithering state & pipe bpc for IGT testing. > This patch will expose the dithering state for the crtc via a debugfs > file "dither". > > Example usage: cat /sys/kernel/debug/dri/0/crtc-0/dither > > Cc: Uma Shankar > Cc: Nischal Varide > Cc: Matt Roper > Signed-off-by: Bhanuprakash Modem > --- > .../drm/i915/display/intel_display_debugfs.c | 32 +++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > index 94e5cbd86e77..a6fefc7d5ab9 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > @@ -2158,11 +2158,43 @@ static const struct { > {"i915_edp_psr_debug", &i915_edp_psr_debug_fops}, > }; > > +static int dither_state_show(struct seq_file *m, void *data) > +{ > + struct intel_crtc *crtc = to_intel_crtc(m->private); > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > + struct intel_crtc_state *crtc_state; > + int ret; > + > + if (!HAS_DISPLAY(dev_priv)) > + return -ENODEV; Unneeded. > + > + ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex); > + if (ret) > + return ret; > + > + crtc_state = to_intel_crtc_state(crtc->base.state); > + seq_printf(m, "bpc: %u\n", crtc_state->pipe_bpp / 3); > + seq_printf(m, "Dither: %u\n", (crtc_state->dither) ? 1 : 0); > + seq_printf(m, "Dither_CC1: %u\n", > + (crtc_state->gamma_mode & GAMMA_MODE_DITHER_AFTER_CC1) ? 1 : 0); Are you looking to duplicate the conditions for enabling this CC1 mode in IGT, and then checking if the driver set the bit as well? I thought the direction has been that we don't do this type of validation in IGT. There is no end to it. Ville? > + > + drm_modeset_unlock(&crtc->base.mutex); > + > + return 0; > +} > +DEFINE_SHOW_ATTRIBUTE(dither_state); > + > void intel_display_debugfs_register(struct drm_i915_private *i915) > { > struct drm_minor *minor = i915->drm.primary; > + struct drm_device *dev = &i915->drm; > + struct drm_crtc *crtc; > int i; > > + drm_for_each_crtc(crtc, dev) > + debugfs_create_file("dither", 0444, crtc->debugfs_entry, crtc, > + &dither_state_fops); > + See intel_crtc_debugfs_add(), called from intel_crtc_late_register(). > for (i = 0; i < ARRAY_SIZE(intel_display_debugfs_files); i++) { > debugfs_create_file(intel_display_debugfs_files[i].name, > S_IRUGO | S_IWUSR, -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx