From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=BAYES_00,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5894BC433E0 for ; Tue, 30 Mar 2021 13:22:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2A0D3619BD for ; Tue, 30 Mar 2021 13:22:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232023AbhC3NVv convert rfc822-to-8bit (ORCPT ); Tue, 30 Mar 2021 09:21:51 -0400 Received: from mail.kernel.org ([198.145.29.99]:55742 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232033AbhC3NVu (ORCPT ); Tue, 30 Mar 2021 09:21:50 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 53B2261994; Tue, 30 Mar 2021 13:21:50 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lREJY-004gaU-Bh; Tue, 30 Mar 2021 14:21:48 +0100 Date: Tue, 30 Mar 2021 14:21:47 +0100 Message-ID: <87im58rd3o.wl-maz@kernel.org> From: Marc Zyngier To: Pali =?UTF-8?B?Um9ow6Fy?= Cc: linux-pci@vger.kernel.org, Marek =?UTF-8?B?QmVow7pu?= Subject: Re: Interrupts in pci-aardvark In-Reply-To: <20210328140912.k33qqfpkizdtlrcp@pali> References: <20210328140912.k33qqfpkizdtlrcp@pali> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: pali@kernel.org, linux-pci@vger.kernel.org, kabel@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Sun, 28 Mar 2021 15:09:12 +0100, Pali Rohár wrote: [...] > Aardvark HW allows to mask summary TOP, summary CORE, individual CORE > (PME, ERR, INTA, INTB, ...), summary MSI and individual MSI bits > interrupts, but not final 16 bit MSI interrupt number. MSI bits are low > 5 bits of 16 bit interrupt number. So it is not possible to mask or > unmask MSI interrupt number X. It is possible to only mask/unmask all > MSI interrupts which low 5 bits is specific value. If you cannot mask individual MSIs, you have two choices: - you only support MSI-X *or* MSI (not multi-MSI) and mask interrupts at the device level - you restrict the number of MSIs to those you can actually control, and that's 2^5 = 32 (which is what the driver currently supports, I believe). > > Also aardvark HW allows to globally enable / disable processing of MSI > interrupts. Masking summary MSI interrupt just cause that GIC does not > trigger it but from registers I can read it (e.g. when GIC calls > aardvark interrupt handler for other non-MSI interrupt). > > And I would like to ask, what is in this hierarchy from kernel point of > view "bottom part of MSI" and what is the "upper part of MSI"? As in > above diagram there are 3 MSI layers. The upper part is the bus-specific part, PCI in your case. You don't need to implement it. The bottom part controls the HW, and deals with all the masking, acknoledgement, allocation and demuxing. > And which irq enable/disable/mask/unmask/ack callbacks I need to > implement for legacy irq, bottom MSI and upper MSI domains? You need to provide what makes sense for your HW. I would guess that you need at least mask/unmask and most probably ack at both levels, and of course a compose_msg callback at the bottom level. > And where should I add code which globally enable/disable receiving of > aardvark MSI interrupts? Currently it is part of aardvark driver probe > function. Seems like the logical place to put it. The kernel deals with individual interrupts, and not with global switches. Thanks, M. -- Without deviation from the norm, progress is not possible.