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From: Jani Nikula <jani.nikula@intel.com>
To: Anshuman Gupta <anshuman.gupta@intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/hdcp: No direct access to power_well desc
Date: Thu, 14 May 2020 13:16:05 +0300	[thread overview]
Message-ID: <87imgy4yai.fsf@intel.com> (raw)
In-Reply-To: <20200513121845.19437-3-anshuman.gupta@intel.com>

On Wed, 13 May 2020, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> HDCP code doesn't require to access power_well internal stuff,
> instead it should use the intel_display_power_well_is_enabled()
> to get the status of desired power_well.
> No functional change.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_hdcp.c | 16 ++++------------
>  1 file changed, 4 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index d0a2bee9035a..409bd5d98a81 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -148,9 +148,8 @@ static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
>  
>  static bool hdcp_key_loadable(struct drm_i915_private *dev_priv)
>  {
> -	struct i915_power_domains *power_domains = &dev_priv->power_domains;
> -	struct i915_power_well *power_well;
>  	enum i915_power_well_id id;
> +	intel_wakeref_t wakeref;
>  	bool enabled = false;
>  
>  	/*
> @@ -162,17 +161,10 @@ static bool hdcp_key_loadable(struct drm_i915_private *dev_priv)
>  	else
>  		id = SKL_DISP_PW_1;
>  
> -	mutex_lock(&power_domains->lock);
> -
>  	/* PG1 (power well #1) needs to be enabled */
> -	for_each_power_well(dev_priv, power_well) {
> -		if (power_well->desc->id == id) {
> -			enabled = power_well->desc->ops->is_enabled(dev_priv,
> -								    power_well);
> -			break;
> -		}
> -	}
> -	mutex_unlock(&power_domains->lock);
> +	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> +	enabled = intel_display_power_well_is_enabled(dev_priv, id);
> +	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);

	with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
		enabled = intel_display_power_well_is_enabled(dev_priv, id);

>  
>  	/*
>  	 * Another req for hdcp key loadability is enabled state of pll for

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2020-05-14 10:16 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-13 12:18 [Intel-gfx] [PATCH 0/2] HDCP minor refactoring Anshuman Gupta
2020-05-13 12:18 ` [Intel-gfx] [PATCH 1/2] drm/i915/hdcp: Add update_pipe early return Anshuman Gupta
2020-05-18 10:14   ` Shankar, Uma
2020-05-18 10:18     ` Gupta, Anshuman
2020-05-13 12:18 ` [Intel-gfx] [PATCH 2/2] drm/i915/hdcp: No direct access to power_well desc Anshuman Gupta
2020-05-14 10:16   ` Jani Nikula [this message]
2020-05-13 15:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success for HDCP minor refactoring Patchwork
2020-05-14 12:03 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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