[U-Boot] [PATCH v2] usb: dwc3: Allocate and flush dwc->ep0_trb in a cache aligned manner

[Felipe Balbi <felipe.balbi@linux.intel.com>]

Hi,

Marek Vasut <marex@denx.de> writes:
> On 10/16/2017 07:21 AM, Faiz Abbas wrote:
>> A flush of the cache is required before any outbound DMA access can
>> take place. The minimum size that can be flushed from the cache is
>> one cache line size. Therefore, any buffer allocated for DMA should
>> be in multiples of cache line size.
>> 
>> Thus, allocate memory for ep0_trb in multiples of cache line size.
>> 
>> Also, when local variable trb is assigned to dwc->ep0_trb[1] and used
>> to flush cache, it leads to cache misaligned messages as only the base
>> address dwc->ep0_trb is cache aligned.
>> 
>> Therefore, flush cache using ep0_trb_addr which is always cache aligned.
>> 
>> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
>
> SGTM, Felipe, can you review this please ?

is cache maintenance done correctly in u-boot? Isn't the whole idea of a
coherent memory area that is is non-cacheable, non-bufferable memory?

Also, why isn't the API itself guaranteeing alignment requirements?

-- 
balbi
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