From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Aneesh Kumar K.V" Date: Mon, 05 May 2014 14:48:12 +0000 Subject: Re: [PATCH 0/6] KVM: PPC: Book3S PR: Add POWER8 support Message-Id: <87iopk9t99.fsf@linux.vnet.ibm.com> List-Id: References: <1398788262-3307-1-git-send-email-agraf@suse.de> <87zjixa4bv.fsf@linux.vnet.ibm.com> <5367737B.1000100@suse.de> <87oazc9toq.fsf@linux.vnet.ibm.com> <5367A33C.8000900@suse.de> In-Reply-To: <5367A33C.8000900@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Alexander Graf Cc: kvm-ppc@vger.kernel.org, kvm@vger.kernel.org Alexander Graf writes: > On 05/05/2014 04:38 PM, Aneesh Kumar K.V wrote: >> Alexander Graf writes: >> >>> On 05/04/2014 06:36 PM, Aneesh Kumar K.V wrote: >>>> Alexander Graf writes: >>>> >>>>> When running on a POWER8 host, we get away with running the guest as POWER7 >>>>> and nothing falls apart. >>>>> >>>>> However, when we start exposing POWER8 as guest CPU, guests will start using >>>>> new abilities on POWER8 which we need to handle. >>>>> >>>>> This patch set does a minimalistic approach to implementing those bits to >>>>> make guests happy enough to run. >>>>> >>>>> >>>>> Alex >>>>> >>>>> Alexander Graf (6): >>>>> KVM: PPC: Book3S PR: Ignore PMU SPRs >>>>> KVM: PPC: Book3S PR: Emulate TIR register >>>>> KVM: PPC: Book3S PR: Handle Facility interrupt and FSCR >>>>> KVM: PPC: Book3S PR: Expose TAR facility to guest >>>>> KVM: PPC: Book3S PR: Expose EBB registers >>>>> KVM: PPC: Book3S PR: Expose TM registers >>>>> >>>>> arch/powerpc/include/asm/kvm_asm.h | 18 ++++--- >>>>> arch/powerpc/include/asm/kvm_book3s_asm.h | 2 + >>>>> arch/powerpc/include/asm/kvm_host.h | 3 ++ >>>>> arch/powerpc/kernel/asm-offsets.c | 3 ++ >>>>> arch/powerpc/kvm/book3s.c | 34 +++++++++++++ >>>>> arch/powerpc/kvm/book3s_emulate.c | 53 ++++++++++++++++++++ >>>>> arch/powerpc/kvm/book3s_hv.c | 30 ----------- >>>>> arch/powerpc/kvm/book3s_pr.c | 82 +++++++++++++++++++++++++++++++ >>>>> arch/powerpc/kvm/book3s_segment.S | 25 ++++++++++ >>>>> 9 files changed, 212 insertions(+), 38 deletions(-) >>>>> >>>> I did most of this as part of >>>> >>>> [RFC PATCH 01/10] KVM: PPC: BOOK3S: PR: Add POWER8 support >>>> http://mid.gmane.org/1390927455-3312-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com >>>> >>>> Any reason why that is not picked up ? TM was the reason I didn't push the >>>> patchset again. I was not sure how to get all the TM details to >>>> work. >>> Ugh, I guess I mostly discarded it as brainstorm patches because they >>> were marked RFC :( >>> >> Do you want me to rework them ?. I guess facility unavailable part and >> TM part in this series are better than what I had. Rest all are more or >> less similar. Or you could cherry pick the SPR handling you haven't >> added yet from this series ? > > I personally refuse to apply patches that are marked RFC, since IMHO on > those the author himself isn't sure he wants them applied yet :). > > I'd say I'll just apply mine after another autotest run and then you > rebase your things on top and fill the gaps with a real, non-RFC patch set. Will do -aneesh From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Aneesh Kumar K.V" Subject: Re: [PATCH 0/6] KVM: PPC: Book3S PR: Add POWER8 support Date: Mon, 05 May 2014 20:18:02 +0530 Message-ID: <87iopk9t99.fsf@linux.vnet.ibm.com> References: <1398788262-3307-1-git-send-email-agraf@suse.de> <87zjixa4bv.fsf@linux.vnet.ibm.com> <5367737B.1000100@suse.de> <87oazc9toq.fsf@linux.vnet.ibm.com> <5367A33C.8000900@suse.de> Mime-Version: 1.0 Content-Type: text/plain Cc: kvm-ppc@vger.kernel.org, kvm@vger.kernel.org To: Alexander Graf Return-path: Received: from e28smtp06.in.ibm.com ([122.248.162.6]:40619 "EHLO e28smtp06.in.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932448AbaEEOsK (ORCPT ); Mon, 5 May 2014 10:48:10 -0400 Received: from /spool/local by e28smtp06.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 5 May 2014 20:18:07 +0530 In-Reply-To: <5367A33C.8000900@suse.de> Sender: kvm-owner@vger.kernel.org List-ID: Alexander Graf writes: > On 05/05/2014 04:38 PM, Aneesh Kumar K.V wrote: >> Alexander Graf writes: >> >>> On 05/04/2014 06:36 PM, Aneesh Kumar K.V wrote: >>>> Alexander Graf writes: >>>> >>>>> When running on a POWER8 host, we get away with running the guest as POWER7 >>>>> and nothing falls apart. >>>>> >>>>> However, when we start exposing POWER8 as guest CPU, guests will start using >>>>> new abilities on POWER8 which we need to handle. >>>>> >>>>> This patch set does a minimalistic approach to implementing those bits to >>>>> make guests happy enough to run. >>>>> >>>>> >>>>> Alex >>>>> >>>>> Alexander Graf (6): >>>>> KVM: PPC: Book3S PR: Ignore PMU SPRs >>>>> KVM: PPC: Book3S PR: Emulate TIR register >>>>> KVM: PPC: Book3S PR: Handle Facility interrupt and FSCR >>>>> KVM: PPC: Book3S PR: Expose TAR facility to guest >>>>> KVM: PPC: Book3S PR: Expose EBB registers >>>>> KVM: PPC: Book3S PR: Expose TM registers >>>>> >>>>> arch/powerpc/include/asm/kvm_asm.h | 18 ++++--- >>>>> arch/powerpc/include/asm/kvm_book3s_asm.h | 2 + >>>>> arch/powerpc/include/asm/kvm_host.h | 3 ++ >>>>> arch/powerpc/kernel/asm-offsets.c | 3 ++ >>>>> arch/powerpc/kvm/book3s.c | 34 +++++++++++++ >>>>> arch/powerpc/kvm/book3s_emulate.c | 53 ++++++++++++++++++++ >>>>> arch/powerpc/kvm/book3s_hv.c | 30 ----------- >>>>> arch/powerpc/kvm/book3s_pr.c | 82 +++++++++++++++++++++++++++++++ >>>>> arch/powerpc/kvm/book3s_segment.S | 25 ++++++++++ >>>>> 9 files changed, 212 insertions(+), 38 deletions(-) >>>>> >>>> I did most of this as part of >>>> >>>> [RFC PATCH 01/10] KVM: PPC: BOOK3S: PR: Add POWER8 support >>>> http://mid.gmane.org/1390927455-3312-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com >>>> >>>> Any reason why that is not picked up ? TM was the reason I didn't push the >>>> patchset again. I was not sure how to get all the TM details to >>>> work. >>> Ugh, I guess I mostly discarded it as brainstorm patches because they >>> were marked RFC :( >>> >> Do you want me to rework them ?. I guess facility unavailable part and >> TM part in this series are better than what I had. Rest all are more or >> less similar. Or you could cherry pick the SPR handling you haven't >> added yet from this series ? > > I personally refuse to apply patches that are marked RFC, since IMHO on > those the author himself isn't sure he wants them applied yet :). > > I'd say I'll just apply mine after another autotest run and then you > rebase your things on top and fill the gaps with a real, non-RFC patch set. Will do -aneesh