From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH 5/5] drm/i915: Dynamically calculate dclv Date: Mon, 28 Jan 2013 14:20:30 +0200 Message-ID: <87ip6hfqi9.fsf@intel.com> References: <1359160867-780-1-git-send-email-ben@bwidawsk.net> <1359160867-780-6-git-send-email-ben@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 021D5E6520 for ; Mon, 28 Jan 2013 04:20:59 -0800 (PST) In-Reply-To: <1359160867-780-6-git-send-email-ben@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Sat, 26 Jan 2013, Ben Widawsky wrote: > Directory CacheLine Valid controls which PDEs are held in the directory > cache. Each bit represents 16 PDEs (16 PDEs at 4 bytes per entry is 1 > cacheline, and therefore, almost makes sense). > > Since we can now have an aliasing PPGTT which isn't 2GB, theoretically, > we should also modify the DCLV value to fit accordingly. > > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +++-- > drivers/gpu/drm/i915/i915_reg.h | 1 - > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index d9af815..168583b 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -344,11 +344,12 @@ void i915_gem_init_ppgtt(struct drm_device *dev) > } > > for_each_ring(ring, dev_priv, i) { > + uint64_t dclv = ppgtt->mapped_size >> 26; > + dclv = (1ULL << dclv) - 1; Maybe add a comment with some of the info from the commit message here? BR, Jani. > if (INTEL_INFO(dev)->gen >= 7) > I915_WRITE(RING_MODE_GEN7(ring), > _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); > - > - I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); > + I915_WRITE(RING_PP_DIR_DCLV(ring), dclv); > I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); > } > } > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 94a08b9..780a715 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -117,7 +117,6 @@ > #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) > #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) > #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) > -#define PP_DIR_DCLV_2G 0xffffffff > > #define GAM_ECOCHK 0x4090 > #define ECOCHK_SNB_BIT (1<<10) > -- > 1.8.1.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx