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b=d9fSGrDe6+scQCeB+gaoCFUSXvwS/dYUToa9WXNtsPm0RUWykOJPfViOGLOK65QqcCPMG/181HpgMunlUftsibPSVozIWg4p3vesPeCAyTqhBFzhxaEfAH/AzuNj2dd9+myOmMzYseFfvS6syDcaKDBEG/vq8pyQzdD1eoIXS2WhG5IZ0bLR/Poow/jQ+BiXRdjhJNx1XFa9cOjJPYflcNE0pOBp3wd9YsU6ngAr9kf2PAYHS83YCbwlqiQ6lmendAgIuBvvic4tj9NfcOl0lnpTeTQKLiKLOERBg7x3Sqo/0H16x0U1Ki+NyTfmAaChoUwRVTMdD3QsgTIDPNlx4A== From: Volodymyr Babchuk To: Mykola Kvach CC: "xen-devel@lists.xenproject.org" , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel Subject: Re: [PATCH v4 1/4] xen/arm: its: initialize host LPI state before activating ITSes Thread-Topic: [PATCH v4 1/4] xen/arm: its: initialize host LPI state before activating ITSes Thread-Index: AQHdUEUSTD/ibdik3UGXPUfUToT1lQ== Date: Tue, 13 Oct 2026 02:36:22 +0000 Message-ID: <87jynmwcm2.fsf@epam.com> References: <0afac276107d8b2a170489950d75e611c69a599b.1790707009.git.mykola_kvach@epam.com> In-Reply-To: <0afac276107d8b2a170489950d75e611c69a599b.1790707009.git.mykola_kvach@epam.com> (Mykola Kvach's message of "Tue, 29 Sep 2026 22:02:10 +0300") Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: user-agent: mu4e 1.14.3; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: VE1PR03MB6078.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8df07605-0243-4fd4-3cba-08df28d2c52d X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Oct 2026 02:36:22.5800 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: yj8pPNqwZTYZukBK8IAuKDnfuyQl0n5bkaIZrn6FDf3UBlp1igYe4AgYKuYafN9TrXEy0gXdOaBYQ0GIXlQyI9iWaVu1B35OkZXH1YULY6E= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR03MB7131 X-purgate-ID: tlsNG-d62444/1791858984-1F66C757-83BAEC3F/0/0 X-purgate-type: clean X-purgate-size: 5996 Hi Mykola, Mykola Kvach writes: > The boot CPU pending table must use the memory attributes selected by > ITS quirks. gicv3_lpi_init_host_lpis() is therefore called after > gicv3_its_init(). However, gicv3_its_init() also programs and enables > each ITS before host LPI state is allocated. No ITS commands are > submitted at that point, but this ordering relies on that implementation > detail. > > Split per-ITS initialization into preparation and activation phases. > First map and disable every ITS and collect its quirks. Then initialize > host LPI state. Only after that, allocate and program the ITS tables and > command queue, and enable each ITS. > > The subsequent gicv3_cpu_init() sequence remains unchanged: it programs > the Redistributor LPI tables, enables LPIs, and then submits the first > MAPC and SYNC commands. > > Suggested-by: Julien Grall > Signed-off-by: Mykola Kvach Reviewed-by: Volodymyr Babchuk > --- > Changes in v4: > - Move the empty ITS list check before the preparation loop. > > Changes in v3: > - New patch implementing the post-4.22 initialization order discussed > during review of the ordering fix. > > Link: https://patchew.org/Xen/341edd8de63dcd84ccc6e7b6c03e9e8fc7105184.17= 81847061.git.mykola._5Fkvach@epam.com/ > --- > xen/arch/arm/gic-v3-its.c | 32 ++++++++++++++++++++++----- > xen/arch/arm/gic-v3.c | 15 ++----------- > xen/arch/arm/include/asm/gic_v3_its.h | 4 ++-- > 3 files changed, 31 insertions(+), 20 deletions(-) > > diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c > index 325835b0ad..511e49a116 100644 > --- a/xen/arch/arm/gic-v3-its.c > +++ b/xen/arch/arm/gic-v3-its.c > @@ -11,6 +11,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -549,10 +550,9 @@ static int gicv3_disable_its(struct host_its *hw_its= ) > return -ETIMEDOUT; > } > =20 > -static int gicv3_its_init_single_its(struct host_its *hw_its) > +static int __init gicv3_its_prepare_single_its(struct host_its *hw_its) > { > - uint64_t reg; > - int i, ret; > + int ret; > =20 > hw_its->its_base =3D ioremap_nocache(hw_its->addr, hw_its->size); > if ( !hw_its->its_base ) > @@ -564,6 +564,14 @@ static int gicv3_its_init_single_its(struct host_its= *hw_its) > =20 > gicv3_its_enable_quirks(hw_its); > =20 > + return 0; > +} > + > +static int __init gicv3_its_init_single_its(struct host_its *hw_its) > +{ > + uint64_t reg; > + int i, ret; > + > reg =3D readq_relaxed(hw_its->its_base + GITS_TYPER); > hw_its->devid_bits =3D GITS_TYPER_DEVICE_ID_BITS(reg); > hw_its->evid_bits =3D GITS_TYPER_EVENT_ID_BITS(reg); > @@ -1189,7 +1197,7 @@ static void gicv3_its_acpi_init(void) > =20 > #endif > =20 > -int gicv3_its_init(void) > +int __init gicv3_its_init(unsigned int host_lpi_bits) > { > struct host_its *hw_its; > int ret; > @@ -1199,15 +1207,29 @@ int gicv3_its_init(void) > else > gicv3_its_acpi_init(); > =20 > + if ( list_empty(&host_its_list) ) > + return 0; > + > list_for_each_entry(hw_its, &host_its_list, entry) > { > - ret =3D gicv3_its_init_single_its(hw_its); > + ret =3D gicv3_its_prepare_single_its(hw_its); > if ( ret ) > return ret; > } > =20 > gicv3_its_validate_quirks(); > =20 > + ret =3D gicv3_lpi_init_host_lpis(host_lpi_bits); > + if ( ret ) > + return ret; > + > + list_for_each_entry(hw_its, &host_its_list, entry) > + { > + ret =3D gicv3_its_init_single_its(hw_its); > + if ( ret ) > + return ret; > + } > + > return 0; > } > =20 > diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c > index acdac22953..6bc3e313be 100644 > --- a/xen/arch/arm/gic-v3.c > +++ b/xen/arch/arm/gic-v3.c > @@ -1984,20 +1984,9 @@ static int __init gicv3_init(void) > =20 > if ( gic_dist_supports_lpis() ) > { > - res =3D gicv3_its_init(); > + res =3D gicv3_its_init(intid_bits); > if ( res ) > - panic("GICv3: ITS: initialization failed: %d\n", res); > - > - /* > - * Host LPI allocation uses ITS-derived memory attributes, so de= fer it > - * until after gicv3_its_init() has discovered ITS workarounds. > - */ > - if ( gicv3_its_host_has_its() ) > - { > - res =3D gicv3_lpi_init_host_lpis(intid_bits); > - if ( res ) > - panic("GICv3: LPI initialization failed: %d\n", res); > - } > + panic("GICv3: ITS/LPI initialization failed: %d\n", res); > } > =20 > res =3D gicv3_cpu_init(); > diff --git a/xen/arch/arm/include/asm/gic_v3_its.h b/xen/arch/arm/include= /asm/gic_v3_its.h > index 02c083f210..e1322b94f8 100644 > --- a/xen/arch/arm/include/asm/gic_v3_its.h > +++ b/xen/arch/arm/include/asm/gic_v3_its.h > @@ -156,7 +156,7 @@ int gicv3_lpi_init_rdist(void __iomem * rdist_base); > =20 > /* Initialize the host structures for LPIs and the host ITSes. */ > int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits); > -int gicv3_its_init(void); > +int gicv3_its_init(unsigned int host_lpi_bits); > =20 > /* Store the physical address and ID for each redistributor as read from= DT. */ > void gicv3_set_redist_address(paddr_t address, unsigned int redist_id); > @@ -245,7 +245,7 @@ static inline int gicv3_lpi_init_host_lpis(unsigned i= nt host_lpi_bits) > return 0; > } > =20 > -static inline int gicv3_its_init(void) > +static inline int gicv3_its_init(unsigned int host_lpi_bits) > { > return 0; > } --=20 WBR, Volodymyr=