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d="scan'208";a="132105311" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2025 04:21:14 -0700 From: Jani Nikula To: Khaled Almahallawy , intel-gfx@lists.freedesktop.org Cc: Khaled Almahallawy , Imre Deak Subject: Re: [PATCH v2] drm/i915/display: Add link rate and lane count to i915_display_info In-Reply-To: <20250401205431.502423-1-khaled.almahallawy@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20250401205431.502423-1-khaled.almahallawy@intel.com> Date: Thu, 03 Apr 2025 14:21:11 +0300 Message-ID: <87jz811oew.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, 01 Apr 2025, Khaled Almahallawy wrote: > Adding link rate and lane count information to i915_display_info makes it > easier and faster to access this data compared to checking kernel logs. > This is particularly beneficial for individuals who are not familiar with > i915 in the following scenarios: > > * Debugging DP tunnel bandwidth usage in the Thunderbolt driver. > * During USB4 certification, it is necessary to know the link rate used by > the monitor to prove that the DP tunnel can handle required rates. > * In PHY CTS, when the connector probes are not mounted correctly, > some display lanes may not appear in the DP Oscilloscope, leading to CTS > failures. > > This change provides validation teams with an easy way to identify and > troubleshoot issues. > > v2: separate seq_printf line (Jani) > > Cc: Imre Deak > Cc: Jani Nikula > Signed-off-by: Khaled Almahallawy > --- > drivers/gpu/drm/i915/display/intel_display_debugfs.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > index 4c784bb7e14b..44df22bd7a18 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > @@ -552,9 +552,11 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc) > seq_printf(m, "\tpipe__mode=" DRM_MODE_FMT "\n", > DRM_MODE_ARG(&crtc_state->hw.pipe_mode)); > > - seq_printf(m, "\tpipe src=" DRM_RECT_FMT ", dither=%s, bpp=%d\n", > + seq_printf(m, "\tpipe src=" DRM_RECT_FMT ", dither=%s, bpp=%d", > DRM_RECT_ARG(&crtc_state->pipe_src), > str_yes_no(crtc_state->dither), crtc_state->pipe_bpp); > + seq_printf(m, ", port_clock=%d, lane_count=%d\n", > + crtc_state->port_clock, crtc_state->lane_count); I did mean separate *output* line, not just source line. > > intel_scaler_info(m, crtc); -- Jani Nikula, Intel