From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B14DEE6420 for ; Thu, 12 Sep 2024 02:16:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3297510E9D0; Thu, 12 Sep 2024 02:16:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="YTmpoWBQ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 05B7A10E9D0 for ; Thu, 12 Sep 2024 02:16:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726107372; x=1757643372; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version:content-transfer-encoding; bh=XH99ubPcXstk30aBZelY+J3xHqyxnU+4ZlWRc9Q0wCc=; b=YTmpoWBQz0HIQZL2gFOECVsdP4cxDm7CLhJlc+UnwI4W1oLKiFjD+jZL Eshr2pJ6VSOL7a0vqRhKE0VAjBBW2WAg0vPfFpdK6wfMZdE1zEa1zu4WA KxA+ak3ZFGzW02I4N63jJEu47Im+MfIsIQt5GYo9cgZ0b6JFLf2xmw30z lLMGdknWyDX977vKEe/8Pe/aXd2JVPD4juWGStQzG+Ezl9EGSczwd63Lb ll29/pQSfk4Nn9LGmqMdFBc2UXxUBlztG46P1h24zfkqJszaX0LNpabTs Y/uUDBn2UGfDJwL7s6S8cV00dFvNyozg7g+vUtuEuV/wIDcjprKczbCPW Q==; X-CSE-ConnectionGUID: cnM5m6aFSta/7/b/cai5eA== X-CSE-MsgGUID: IXklpZr4TPefx3t2Uit8Yg== X-IronPort-AV: E=McAfee;i="6700,10204,11192"; a="42413636" X-IronPort-AV: E=Sophos;i="6.10,221,1719903600"; d="scan'208";a="42413636" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2024 19:16:12 -0700 X-CSE-ConnectionGUID: FkoIBE1rTk6e0a9g+t5SPg== X-CSE-MsgGUID: uTE/6bd/QHmAPr9SOxW5Rw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,221,1719903600"; d="scan'208";a="68346771" Received: from ktalukda-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.125.81.26]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2024 19:16:11 -0700 Date: Wed, 11 Sep 2024 19:13:57 -0700 Message-ID: <87jzfh39ga.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: =?ISO-8859-1?Q?Jos=E9?= Roberto de Souza Cc: Subject: Re: [PATCH 2/3] drm/xe: Add a parameter to xe_bb_create_job() to append or not batch buffer end instruction In-Reply-To: <20240911200218.130219-2-jose.souza@intel.com> References: <20240911200218.130219-1-jose.souza@intel.com> <20240911200218.130219-2-jose.souza@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Wed, 11 Sep 2024 13:02:17 -0700, Jos=E9 Roberto de Souza wrote: > Hi Jose, > There is overflow happening in OA because it reuses batch buffers, > so at each submission one batch buffer end instruction is appended > eventually causing a overflow. > That will be fixed in the next patch, here just adding adding > parameter and updating all the callers. Thanks for finding this, this is indeed a bug. However I have a much simpler fix, which is just the patch below (instead of your two patches): diff --git a/drivers/gpu/drm/xe/xe_bb.c b/drivers/gpu/drm/xe/xe_bb.c index a13e0b3a169ed..148ccae265b47 100644 --- a/drivers/gpu/drm/xe/xe_bb.c +++ b/drivers/gpu/drm/xe/xe_bb.c @@ -65,7 +65,8 @@ __xe_bb_create_job(struct xe_exec_queue *q, struct xe_bb = *bb, u64 *addr) { u32 size =3D drm_suballoc_size(bb->bo); =20 - bb->cs[bb->len++] =3D MI_BATCH_BUFFER_END; + if (bb->cs[bb->len] !=3D MI_BATCH_BUFFER_END) + bb->cs[bb->len++] =3D MI_BATCH_BUFFER_END; =20 xe_gt_assert(q->gt, bb->len * 4 + bb_prefetch(q->gt) <=3D size); So just append MI_BATCH_BUFFER_END if it is not already there. Also, MI_BATCH_BUFFER_END can be added by the caller, otherwise the callee will add that. Thoughts? Please send this patch if you agree, I'll R-b it. Thanks. -- Ashutosh