From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4EBBFECAAD3 for ; Fri, 9 Sep 2022 08:50:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 46A1610EC12; Fri, 9 Sep 2022 08:50:27 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id A323710EC12 for ; Fri, 9 Sep 2022 08:50:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662713422; x=1694249422; h=from:to:subject:in-reply-to:references:date:message-id: mime-version:content-transfer-encoding; bh=KgaJFpou5qn35CmhJDfSEyLT6ULZR8HeiMn6NVJGmDQ=; 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charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use REG_FIELD_GET() to extract skl+ wm latencies X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, 08 Sep 2022, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > Replace the hand rolled stuff with REG_FIELD_GET() for reading > out the skl+ watermark latencies. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/skl_watermark.c | 22 +++++++------------- > drivers/gpu/drm/i915/i915_reg.h | 8 +++---- > 2 files changed, 12 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/d= rm/i915/display/skl_watermark.c > index 25ca92ae8958..cb297725d5b9 100644 > --- a/drivers/gpu/drm/i915/display/skl_watermark.c > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c > @@ -3239,13 +3239,10 @@ static void skl_read_wm_latency(struct drm_i915_p= rivate *i915, u16 wm[]) > return; > } >=20=20 > - wm[0] =3D (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > - wm[1] =3D ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > - wm[2] =3D ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > - wm[3] =3D ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > + wm[0] =3D REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult; > + wm[1] =3D REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult; > + wm[2] =3D REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult; > + wm[3] =3D REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult; >=20=20 > /* read the second set of memory latencies[4:7] */ > val =3D 1; /* data0 to be programmed to 1 for second set */ > @@ -3255,13 +3252,10 @@ static void skl_read_wm_latency(struct drm_i915_p= rivate *i915, u16 wm[]) > return; > } >=20=20 > - wm[4] =3D (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > - wm[5] =3D ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > - wm[6] =3D ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > - wm[7] =3D ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > + wm[4] =3D REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult; > + wm[5] =3D REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult; > + wm[6] =3D REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult; > + wm[7] =3D REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult; >=20=20 > adjust_wm_latency(i915, wm, max_level, read_latency); > } > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index c413eec3373f..7289e2b7da2c 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6551,10 +6551,10 @@ > #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) > #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 > #define GEN9_PCODE_READ_MEM_LATENCY 0x6 > -#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF > -#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 > -#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 > -#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 > +#define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24) > +#define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16) > +#define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8) > +#define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0) > #define SKL_PCODE_LOAD_HDCP_KEYS 0x5 > #define SKL_PCODE_CDCLK_CONTROL 0x7 > #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 --=20 Jani Nikula, Intel Open Source Graphics Center