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Wed, 09 Dec 2020 08:14:38 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id z13sm4594878wmz.3.2020.12.09.08.14.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Dec 2020 08:14:37 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 6D7FD1FF7E; Wed, 9 Dec 2020 16:14:36 +0000 (GMT) References: <20201208194839.31305-1-cfontana@suse.de> <20201208194839.31305-21-cfontana@suse.de> <87czzjdxsx.fsf@linaro.org> User-agent: mu4e 1.5.7; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Claudio Fontana Subject: Re: [RFC v9 20/32] cpu: Move tlb_fill to tcg_ops Date: Wed, 09 Dec 2020 16:12:40 +0000 In-reply-to: Message-ID: <87k0trc5xv.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x443.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Durrant , Jason Wang , qemu-devel@nongnu.org, Peter Xu , haxm-team@intel.com, Colin Xu , Olaf Hering , Stefano Stabellini , Bruce Rogers , "Emilio G . Cota" , Anthony Perard , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Laurent Vivier , Thomas Huth , Eduardo Habkost , Richard Henderson , Cameron Esfahani , Dario Faggioli , Roman Bolshakov , Sunil Muthuswamy , Marcelo Tosatti , Wenchao Wang , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Claudio Fontana writes: > On 12/9/20 12:26 PM, Alex Benn=C3=A9e wrote: >>=20 >> Claudio Fontana writes: >>=20 >>> From: Eduardo Habkost >>> >>> Signed-off-by: Eduardo Habkost >>> [claudio: wrapped in CONFIG_TCG] >>> Signed-off-by: Claudio Fontana >>> Reviewed-by: Philippe Mathieu-Daud=C3=A9 >>> --- >>> accel/tcg/cputlb.c | 6 +++--- >>> accel/tcg/user-exec.c | 6 +++--- >>> include/hw/core/cpu.h | 9 --------- >>> include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++ >>> target/alpha/cpu.c | 2 +- >>> target/arm/cpu.c | 2 +- >>> target/avr/cpu.c | 2 +- >>> target/cris/cpu.c | 2 +- >>> target/hppa/cpu.c | 2 +- >>> target/i386/tcg-cpu.c | 2 +- >>> target/lm32/cpu.c | 2 +- >>> target/m68k/cpu.c | 2 +- >>> target/microblaze/cpu.c | 2 +- >>> target/mips/cpu.c | 2 +- >>> target/moxie/cpu.c | 2 +- >>> target/nios2/cpu.c | 2 +- >>> target/openrisc/cpu.c | 2 +- >>> target/ppc/translate_init.c.inc | 2 +- >>> target/riscv/cpu.c | 2 +- >>> target/rx/cpu.c | 2 +- >>> target/s390x/cpu.c | 2 +- >>> target/sh4/cpu.c | 2 +- >>> target/sparc/cpu.c | 2 +- >>> target/tilegx/cpu.c | 2 +- >>> target/tricore/cpu.c | 2 +- >>> target/unicore32/cpu.c | 2 +- >>> target/xtensa/cpu.c | 2 +- >>> 27 files changed, 41 insertions(+), 38 deletions(-) >>> >>> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c >>> index 42ab79c1a5..2dc71b5528 100644 >>> --- a/accel/tcg/cputlb.c >>> +++ b/accel/tcg/cputlb.c >>> @@ -1286,7 +1286,7 @@ static void tlb_fill(CPUState *cpu, target_ulong = addr, int size, >>> * This is not a probe, so only valid return is success; failure >>> * should result in exception + longjmp to the cpu loop. >>> */ >>> - ok =3D cc->tlb_fill(cpu, addr, size, access_type, mmu_idx, false, = retaddr); >>> + ok =3D cc->tcg_ops.tlb_fill(cpu, addr, size, access_type, mmu_idx,= false, retaddr); >>> assert(ok); >>> } >>>=20=20 >>> @@ -1557,8 +1557,8 @@ static int probe_access_internal(CPUArchState *en= v, target_ulong addr, >>> CPUState *cs =3D env_cpu(env); >>> CPUClass *cc =3D CPU_GET_CLASS(cs); >>>=20=20 >>> - if (!cc->tlb_fill(cs, addr, fault_size, access_type, >>> - mmu_idx, nonfault, retaddr)) { >>> + if (!cc->tcg_ops.tlb_fill(cs, addr, fault_size, access_typ= e, >>> + mmu_idx, nonfault, retaddr)) { >>> /* Non-faulting page table read failed. */ >>> *phost =3D NULL; >>> return TLB_INVALID_MASK; >>> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c >>> index 4ebe25461a..7f53992251 100644 >>> --- a/accel/tcg/user-exec.c >>> +++ b/accel/tcg/user-exec.c >>> @@ -186,7 +186,7 @@ static inline int handle_cpu_signal(uintptr_t pc, s= iginfo_t *info, >>> clear_helper_retaddr(); >>>=20=20 >>> cc =3D CPU_GET_CLASS(cpu); >>> - cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc= ); >>> + cc->tcg_ops.tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, f= alse, pc); >>> g_assert_not_reached(); >>> } >>>=20=20 >>> @@ -216,8 +216,8 @@ static int probe_access_internal(CPUArchState *env,= target_ulong addr, >>> } else { >>> CPUState *cpu =3D env_cpu(env); >>> CPUClass *cc =3D CPU_GET_CLASS(cpu); >>> - cc->tlb_fill(cpu, addr, fault_size, access_type, >>> - MMU_USER_IDX, false, ra); >>> + cc->tcg_ops.tlb_fill(cpu, addr, fault_size, access_type, >>> + MMU_USER_IDX, false, ra); >>> g_assert_not_reached(); >>> } >>> } >>> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h >>> index 52142e9094..c82ef261c6 100644 >>> --- a/include/hw/core/cpu.h >>> +++ b/include/hw/core/cpu.h >>> @@ -110,12 +110,6 @@ struct TranslationBlock; >>> * If the target behaviour here is anything other than "set >>> * the PC register to the value passed in" then the target must >>> * also implement the synchronize_from_tb hook. >>> - * @tlb_fill: Callback for handling a softmmu tlb miss or user-only >>> - * address fault. For system mode, if the access is valid, call >>> - * tlb_set_page and return true; if the access is invalid, and >>> - * probe is true, return false; otherwise raise an exception and >>> - * do not return. For user-only mode, always raise an exception >>> - * and do not return. >>> * @get_phys_page_debug: Callback for obtaining a physical address. >>> * @get_phys_page_attrs_debug: Callback for obtaining a physical addre= ss and the >>> * associated memory transaction attributes to use for the acces= s. >>> @@ -183,9 +177,6 @@ struct CPUClass { >>> void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, >>> Error **errp); >>> void (*set_pc)(CPUState *cpu, vaddr value); >>> - bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, >>> - MMUAccessType access_type, int mmu_idx, >>> - bool probe, uintptr_t retaddr); >>> hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); >>> hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, >>> MemTxAttrs *attrs); >>> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-op= s.h >>> index e12f32919b..2ea94acca0 100644 >>> --- a/include/hw/core/tcg-cpu-ops.h >>> +++ b/include/hw/core/tcg-cpu-ops.h >>> @@ -37,6 +37,18 @@ typedef struct TcgCpuOperations { >>> void (*cpu_exec_exit)(CPUState *cpu); >>> /** @cpu_exec_interrupt: Callback for processing interrupts in cpu= _exec */ >>> bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); >>> + /** >>> + * @tlb_fill: Handle a softmmu tlb miss or user-only address fault >>> + * >>> + * For system mode, if the access is valid, call tlb_set_page >>> + * and return true; if the access is invalid, and probe is >>> + * true, return false; otherwise raise an exception and do >>> + * not return. For user-only mode, always raise an exception >>> + * and do not return. >>> + */ >>> + bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, >>> + MMUAccessType access_type, int mmu_idx, >>> + bool probe, uintptr_t retaddr); >>=20 >> As per previous patch, here is a chance to clean-up the comment. > > > Could you provide the text? I think you understand this better than I > do... As Eduardo pointed out the kernel-doc pass won't work with in-line functions unless they are extracted and typedefed which seems excessive considering we don't currently generate docs from these headers. Ignore the request. > > >>=20 >> Otherwise: >>=20 >> Reviewed-by: Alex Benn=C3=A9e >>=20 > > Thanks! > > Claudio --=20 Alex Benn=C3=A9e