From: Esben Haabendal <esben.haabendal@gmail.com>
To: Chuanhua Han <chuanhua.han@nxp.com>
Cc: broonie@kernel.org, linux-spi@vger.kernel.org,
linux-kernel@vger.kernel.org, boris.brezillon@bootlin.com
Subject: Re: [PATCH v2 4/4] spi: spi-fsl-dspi: Fix adjust the byte order when sending and receiving data
Date: Sun, 30 Sep 2018 12:27:24 +0200 [thread overview]
Message-ID: <87k1n3701f.fsf@gmail.com> (raw)
In-Reply-To: <20180930092535.24544-4-chuanhua.han@nxp.com> (Chuanhua Han's message of "Sun, 30 Sep 2018 17:25:35 +0800")
Chuanhua Han <chuanhua.han@nxp.com> writes:
> This patch fixes the byte order inversion problem in the XSPI mode of
> the dspi controller during data transfer.
> In XSPI mode,When I read and write data without converting the byte
> order of the data, and read and write the data directly, I tested spi
> flash connected by the dspi controller and found that the byte
> order of the data was reversed by the correct byte order.
> When I changed the byte order according to the SPIx_CTARn[LSBFE] flag,
> the correct data was obtained.
I believe this is related to patch 1/4 of this series, and your attempt
on pushing the 8-bit spi-mem data into 32-bit SPI words. The
byte-ordering for that does not belong here, and will likely break
byte-ordering for other (proper) use of XSPI mode.
My advice is that you focus your effort on implementing/fixing DMA mode,
ie. erratum A-011218.
A proper implementation of that will be appreciated, and should give you
much better performance than XSPI mode would be able to give you.
/Esben
next prev parent reply other threads:[~2018-09-30 10:27 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-30 9:25 [PATCH v2 1/4] spi: spi-mem: Add the spi_set_xfer_bpw function Chuanhua Han
2018-09-30 9:25 ` [PATCH v2 2/4] spi: spi-fsl-dspi: Fix delete the processing of undefined bitmask for rxdata Chuanhua Han
2018-09-30 10:06 ` Boris Brezillon
2018-09-30 10:10 ` Chuanhua Han
2018-09-30 10:17 ` Boris Brezillon
2018-09-30 10:37 ` Chuanhua Han
2018-09-30 10:37 ` Esben Haabendal
2018-09-30 10:41 ` Boris Brezillon
2018-09-30 10:29 ` Esben Haabendal
2018-09-30 9:25 ` [PATCH v2 3/4] spi: spi-fsl-dspi: Fix cmd_fifo is written before tx_fifo Chuanhua Han
2018-09-30 10:30 ` Esben Haabendal
2018-09-30 9:25 ` [PATCH v2 4/4] spi: spi-fsl-dspi: Fix adjust the byte order when sending and receiving data Chuanhua Han
2018-09-30 10:27 ` Esben Haabendal [this message]
2018-09-30 10:04 ` [PATCH v2 1/4] spi: spi-mem: Add the spi_set_xfer_bpw function Boris Brezillon
2018-09-30 10:17 ` Esben Haabendal
2018-09-30 10:40 ` Chuanhua Han
2018-09-30 10:18 ` Chuanhua Han
2018-09-30 10:40 ` Boris Brezillon
2018-09-30 10:48 ` Chuanhua Han
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