From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mika Kuoppala Subject: Re: [PATCH] drm/i915: Perform an invalidate prior to executing golden renderstate Date: Tue, 08 Aug 2017 16:36:39 +0300 Message-ID: <87k22e5ggo.fsf@gaia.fi.intel.com> References: <20170808131904.1385-1-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id E60B98994D for ; Tue, 8 Aug 2017 13:37:53 +0000 (UTC) In-Reply-To: <20170808131904.1385-1-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Chris Wilson , intel-gfx@lists.freedesktop.org Cc: stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org Q2hyaXMgV2lsc29uIDxjaHJpc0BjaHJpcy13aWxzb24uY28udWs+IHdyaXRlczoKCj4gQXMgd2Ug bWF5IGhhdmUganVzdCBib3VuZCB0aGUgcmVuZGVyc3RhdGUgaW50byB0aGUgR0dUVCBmb3IgZXhl Y3V0aW9uLCB3ZQo+IG5lZWQgdG8gZW5zdXJlIHRoYXQgdGhlIEdUVCBUTEIgYXJlIGFsc28gZmx1 c2hlZC4KPgo+IE9uIHNuYi1ndDIsIHRoaXMgd291bGQgY2F1c2UgYSByYW5kb20gR1BVIGhhbmcg YXQgdGhlIHN0YXJ0IG9mIGEgbmV3Cj4gY29udGV4dCAoZS5nLiBib290KSBhbmQgb24gc25iLWd0 MSwgaXQgd2FzIGNhdXNpbmcgdGhlIHJlbmRlcnN0YXRlIGJhdGNoCj4gdG8gdGFrZSB+MTBzLiBJ dCB3YXMgdGhlIEdQVSBoYW5nIHRoYXQgcmV2ZWFsZWQgdGhlIHRydXRoLCBhcyB0aGUgQ1MKPiBn bGVlZnVsbHkgZXhlY3V0ZWQgYmV5b25kIHRoZSBlbmQgb2YgdGhlIGdvbGRlbiByZW5kZXJzdGF0 ZSBiYXRjaCwgYSBnb29kCj4gaW5kaWNhdG9yIGZvciBhIEdUVCBUTEIgbWlzcy4KPgo+IFNpZ25l ZC1vZmYtYnk6IENocmlzIFdpbHNvbiA8Y2hyaXNAY2hyaXMtd2lsc29uLmNvLnVrPgo+IENjOiBN aWthIEt1b3BwYWxhIDxtaWthLmt1b3BwYWxhQGxpbnV4LmludGVsLmNvbT4KPiBDYzogc3RhYmxl QHZnZXIua2VybmVsLm9yZwoKVGhlIGZsdXNoIGhhcyBiZWVuIHRoZXJlIGJ1dCBnb3Qgc3RvbXBl ZCBieToKCkZpeGVzOiBkYzRiZTYwNzFhMjQgKCJkcm0vaTkxNTogQWRkIGV4cGxpY2l0IHJlcXVl c3QgbWFuYWdlbWVudCB0byBpOTE1X2dlbV9pbml0X2h3KCkiKQoKTm93IHdlIGNhbiBmaXggdGhl IGdlbjYgcmVuZGVyc3RhdGUgdG9vIDspCgpSZXZpZXdlZC1ieTogTWlrYSBLdW9wcGFsYSA8bWlr YS5rdW9wcGFsYUBpbnRlbC5jb20+Cgo+IC0tLQo+ICBkcml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1 X2dlbV9yZW5kZXJfc3RhdGUuYyB8IDQgKysrKwo+ICAxIGZpbGUgY2hhbmdlZCwgNCBpbnNlcnRp b25zKCspCj4KPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9nZW1fcmVu ZGVyX3N0YXRlLmMgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1X2dlbV9yZW5kZXJfc3RhdGUu Ywo+IGluZGV4IDI0MWQ4MjdiODVmYi4uMzcwM2RjOTFlZWRhIDEwMDY0NAo+IC0tLSBhL2RyaXZl cnMvZ3B1L2RybS9pOTE1L2k5MTVfZ2VtX3JlbmRlcl9zdGF0ZS5jCj4gKysrIGIvZHJpdmVycy9n cHUvZHJtL2k5MTUvaTkxNV9nZW1fcmVuZGVyX3N0YXRlLmMKPiBAQCAtMjQyLDYgKzI0MiwxMCBA QCBpbnQgaTkxNV9nZW1fcmVuZGVyX3N0YXRlX2VtaXQoc3RydWN0IGRybV9pOTE1X2dlbV9yZXF1 ZXN0ICpyZXEpCj4gIAkJCWdvdG8gZXJyX3VucGluOwo+ICAJfQo+ICAKPiArCXJldCA9IHJlcS0+ ZW5naW5lLT5lbWl0X2ZsdXNoKHJlcSwgRU1JVF9JTlZBTElEQVRFKTsKPiArCWlmIChyZXQpCj4g KwkJZ290byBlcnJfdW5waW47Cj4gKwo+ICAJcmV0ID0gcmVxLT5lbmdpbmUtPmVtaXRfYmJfc3Rh cnQocmVxLAo+ICAJCQkJCSBzby0+YmF0Y2hfb2Zmc2V0LCBzby0+YmF0Y2hfc2l6ZSwKPiAgCQkJ CQkgSTkxNV9ESVNQQVRDSF9TRUNVUkUpOwo+IC0tIAo+IDIuMTMuMwpfX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpJbnRlbC1nZnggbWFpbGluZyBsaXN0Cklu dGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5v cmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com ([192.55.52.120]:38286 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752133AbdHHNhx (ORCPT ); Tue, 8 Aug 2017 09:37:53 -0400 From: Mika Kuoppala To: Chris Wilson , intel-gfx@lists.freedesktop.org Cc: Chris Wilson , stable@vger.kernel.org Subject: Re: [PATCH] drm/i915: Perform an invalidate prior to executing golden renderstate In-Reply-To: <20170808131904.1385-1-chris@chris-wilson.co.uk> References: <20170808131904.1385-1-chris@chris-wilson.co.uk> Date: Tue, 08 Aug 2017 16:36:39 +0300 Message-ID: <87k22e5ggo.fsf@gaia.fi.intel.com> MIME-Version: 1.0 Content-Type: text/plain Sender: stable-owner@vger.kernel.org List-ID: Chris Wilson writes: > As we may have just bound the renderstate into the GGTT for execution, we > need to ensure that the GTT TLB are also flushed. > > On snb-gt2, this would cause a random GPU hang at the start of a new > context (e.g. boot) and on snb-gt1, it was causing the renderstate batch > to take ~10s. It was the GPU hang that revealed the truth, as the CS > gleefully executed beyond the end of the golden renderstate batch, a good > indicator for a GTT TLB miss. > > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala > Cc: stable@vger.kernel.org The flush has been there but got stomped by: Fixes: dc4be6071a24 ("drm/i915: Add explicit request management to i915_gem_init_hw()") Now we can fix the gen6 renderstate too ;) Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/i915_gem_render_state.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c > index 241d827b85fb..3703dc91eeda 100644 > --- a/drivers/gpu/drm/i915/i915_gem_render_state.c > +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c > @@ -242,6 +242,10 @@ int i915_gem_render_state_emit(struct drm_i915_gem_request *req) > goto err_unpin; > } > > + ret = req->engine->emit_flush(req, EMIT_INVALIDATE); > + if (ret) > + goto err_unpin; > + > ret = req->engine->emit_bb_start(req, > so->batch_offset, so->batch_size, > I915_DISPATCH_SECURE); > -- > 2.13.3