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From: Jani Nikula <jani.nikula@intel.com>
To: "Chauhan, Madhav" <madhav.chauhan@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Cc: "Conselvan De Oliveira,
	Ander" <ander.conselvan.de.oliveira@intel.com>,
	"Kumar, Shobhit" <shobhit.kumar@intel.com>,
	"Tsou, Vincente" <vincente.tsou@intel.com>
Subject: Re: [GLK MIPI DSI V2 9/9] drm/915: Parsing the missed out DTD fields from the VBT
Date: Thu, 22 Dec 2016 15:43:15 +0200	[thread overview]
Message-ID: <87k2askrkc.fsf@intel.com> (raw)
In-Reply-To: <FDE0F82259988449BC0C053E4EF090C947FC17CD@BGSMSX104.gar.corp.intel.com>

On Thu, 22 Dec 2016, "Chauhan, Madhav" <madhav.chauhan@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani
>> Sent: Thursday, December 22, 2016 5:09 PM
>> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Cc: Conselvan De Oliveira, Ander <ander.conselvan.de.oliveira@intel.com>;
>> Saarinen, Jani <jani.saarinen@intel.com>; Konduru, Chandra
>> <chandra.konduru@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
>> Mukherjee, Indranil <indranil.mukherjee@intel.com>; Kumar, Shobhit
>> <shobhit.kumar@intel.com>; Tsou, Vincente <vincente.tsou@intel.com>;
>> Chauhan, Madhav <madhav.chauhan@intel.com>
>> Subject: Re: [GLK MIPI DSI V2 9/9] drm/915: Parsing the missed out DTD
>> fields from the VBT
>> 
>> On Thu, 15 Dec 2016, Madhav Chauhan <madhav.chauhan@intel.com>
>> wrote:
>> > From: Vincente Tsou <vincente.tsou@intel.com>
>> >
>> > The upper bits of the vsync width, vsync offset and hsync width were
>> > not parsed form the VBT. Parse these fields in this patch.
>> >
>> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> > Signed-off-by: Vincente Tsou <vincente.tsou@intel.com>
>> 
>> The author Signed-off-by should be first, others are added below.
>> 
>> > ---
>> >  drivers/gpu/drm/i915/intel_bios.c     | 8 +++++---
>> >  drivers/gpu/drm/i915/intel_vbt_defs.h | 6 ++++--
>> >  2 files changed, 9 insertions(+), 5 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_bios.c
>> > b/drivers/gpu/drm/i915/intel_bios.c
>> > index eaade27..e1d014b 100644
>> > --- a/drivers/gpu/drm/i915/intel_bios.c
>> > +++ b/drivers/gpu/drm/i915/intel_bios.c
>> > @@ -114,16 +114,18 @@ static u32 get_blocksize(const void *block_data)
>> >  	panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +
>> >  		((dvo_timing->hsync_off_hi << 8) | dvo_timing-
>> >hsync_off_lo);
>> >  	panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
>> > -		dvo_timing->hsync_pulse_width;
>> > +		((dvo_timing->hsync_pulse_width_hi << 8) |
>> > +				    dvo_timing->hsync_pulse_width);
>> >  	panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +
>> >  		((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo);
>> >
>> >  	panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) |
>> >  		dvo_timing->vactive_lo;
>> >  	panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +
>> > -		dvo_timing->vsync_off;
>> > +		((dvo_timing->vsync_off_hi << 4) | dvo_timing->vsync_off);
>> >  	panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +
>> > -		dvo_timing->vsync_pulse_width;
>> > +		((dvo_timing->vsync_pulse_width_hi << 4) |
>> > +				    dvo_timing->vsync_pulse_width);
>> 
>> The indentation for the above changes seem to be off.
>> 
>> >  	panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay +
>> >  		((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo);
>> >  	panel_fixed_mode->clock = dvo_timing->clock * 10; diff --git
>> > a/drivers/gpu/drm/i915/intel_vbt_defs.h
>> > b/drivers/gpu/drm/i915/intel_vbt_defs.h
>> > index 8886cab1..bf9d2d3 100644
>> > --- a/drivers/gpu/drm/i915/intel_vbt_defs.h
>> > +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
>> > @@ -402,7 +402,9 @@ struct lvds_dvo_timing {
>> >  	u8 hsync_pulse_width;
>> >  	u8 vsync_pulse_width:4;
>> >  	u8 vsync_off:4;
>> > -	u8 rsvd0:6;
>> > +	u8 vsync_pulse_width_hi:2;
>> > +	u8 vsync_off_hi:2;
>> > +	u8 hsync_pulse_width_hi:2;
>> 
>> Please rename the lo counterparts of these fields to have _lo suffix, for
>> consistency with other hi/lo split fields. With that, the compiler will help you
>> in making sure you found all the places you need to fix. ;)
>> 
>> >  	u8 hsync_off_hi:2;
>> >  	u8 himage_lo;
>> >  	u8 vimage_lo;
>> > @@ -414,7 +416,7 @@ struct lvds_dvo_timing {
>> >  	u8 digital:2;
>> >  	u8 vsync_positive:1;
>> >  	u8 hsync_positive:1;
>> > -	u8 rsvd2:1;
>> > +	u8 interlaced:1;
>> 
>> This should be non_interlaced, as that's how the bit is defined.
>> 
>> Otherwise, seems like a good find.
>
> Thanks Jani for review. Will address the review comment and resend it.

Please send it as a separate patch outside of this series, it's not
really related.

BR,
Jani.


>
>> 
>> BR,
>> Jani.
>> 
>> >  } __packed;
>> >
>> >  struct lvds_pnp_id {
>> 
>> --
>> Jani Nikula, Intel Open Source Technology Center

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
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  reply	other threads:[~2016-12-22 13:43 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-12-15  9:01 [GLK MIPI DSI V2 0/9] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
2016-12-15  9:01 ` [GLK MIPI DSI V2 1/9] drm/i915/glk: Add new bit fields in MIPI CTRL register Madhav Chauhan
2016-12-23 13:54   ` Jani Nikula
2016-12-15  9:01 ` [GLK MIPI DSI V2 2/9] drm/i915/glk: Program new MIPI DSI PHY registers for GLK Madhav Chauhan
2016-12-22 12:02   ` Ville Syrjälä
2016-12-22 12:28     ` Jani Nikula
2016-12-23 13:57   ` Jani Nikula
2016-12-23 19:22     ` Chauhan, Madhav
2016-12-26 12:49       ` Chauhan, Madhav
2016-12-15  9:01 ` [GLK MIPI DSI V2 3/9] drm/i915/glk: Add MIPIIO Enable/disable sequence Madhav Chauhan
2016-12-23 14:09   ` Jani Nikula
2016-12-26 12:05     ` Chauhan, Madhav
2016-12-27 12:34       ` Jani Nikula
2016-12-27 13:32         ` Chauhan, Madhav
2016-12-27 14:47           ` Jani Nikula
2016-12-27 15:43             ` Chauhan, Madhav
2016-12-15  9:01 ` [GLK MIPI DSI V2 4/9] drm/i915: Set the Z inversion overlap field Madhav Chauhan
2016-12-15  9:01 ` [GLK MIPI DSI V2 5/9] drm/i915/glk: Add DSI PLL divider range for glk Madhav Chauhan
2016-12-15  9:01 ` [GLK MIPI DSI V2 6/9] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT Madhav Chauhan
2016-12-15  9:01 ` [GLK MIPI DSI V2 7/9] drm/i915/glk: Program txesc clock divider for GLK Madhav Chauhan
2016-12-15  9:01 ` [GLK MIPI DSI V2 8/9] drm/i915/glk: Program dphy param reg " Madhav Chauhan
2016-12-15  9:01 ` [GLK MIPI DSI V2 9/9] drm/915: Parsing the missed out DTD fields from the VBT Madhav Chauhan
2016-12-22 11:39   ` Jani Nikula
2016-12-22 13:16     ` Chauhan, Madhav
2016-12-22 13:43       ` Jani Nikula [this message]
2016-12-22 15:43         ` Chauhan, Madhav
2016-12-15  9:45 ` ✓ Fi.CI.BAT: success for GLK MIPI DSI VIDEO MODE PATCHES (rev2) Patchwork

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