From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mika Kuoppala Subject: Re: [PATCH] drm/i915: Unconditionally flush any chipset buffers before execbuf Date: Tue, 16 Aug 2016 17:01:51 +0300 Message-ID: <87k2fgolrk.fsf@gaia.fi.intel.com> References: <1471349672-9645-1-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id A80066E399 for ; Tue, 16 Aug 2016 14:02:49 +0000 (UTC) In-Reply-To: <1471349672-9645-1-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Chris Wilson , intel-gfx@lists.freedesktop.org Cc: Daniel Vetter , Akash Goel , stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org Q2hyaXMgV2lsc29uIDxjaHJpc0BjaHJpcy13aWxzb24uY28udWs+IHdyaXRlczoKCj4gSWYgdXNl cnNwYWNlIGlzIGFzeW5jaHJvbm91c2x5IHN0cmVhbWluZyBpbnRvIHRoZSBiYXRjaCBvciBvdGhl cgo+IGV4ZWNvYmplY3RzLCB3ZSBtYXkgbm90IGZsdXNoIHRob3NlIHdyaXRlcyBhbG9uZyB3aXRo IGEgY2hhbmdlIGluIGNhY2hlCj4gZG9tYWluIChhcyB0aGVyZSBpcyBubyBjaGFuZ2UpLiBUaGVy ZWZvcmUgdGhvc2Ugd3JpdGVzIG1heSBlbmQgdXAgaW4KPiBpbnRlcm5hbCBjaGlwc2V0IGJ1ZmZl cnMgYW5kIG5vdCB2aXNpYmxlIHRvIHRoZSBHUFUgdXBvbiBleGVjdXRpb24uIFdlCj4gbXVzdCBp c3N1ZSBhIGZsdXNoIGNvbW1hbmQgb3Igb3RoZXJ3aXNlIHdlIGVuY291bnRlciBpbmNvaGVyZW5j eSBpbiB0aGUKPiBiYXRjaGJ1ZmZlcnMgYW5kIHRoZSBHUFUgZXhlY3V0aW5nIGludmFsaWQgY29t bWFuZHMgKGkuZS4gaGFuZ2luZykgcXVpdGUKPiByZWd1bGFybHkuCj4KPiBCdWd6aWxsYTogaHR0 cHM6Ly9idWdzLmZyZWVkZXNrdG9wLm9yZy9zaG93X2J1Zy5jZ2k/aWQ9OTA4NDEKPiBGaXhlczog MTgxNmY5MjM2MzAzICgiZHJtL2k5MTU6IFN1cHBvcnQgY3JlYXRpb24gb2YgdW5ib3VuZCB3YyB1 c2VyLi4uIikKPiBTaWduZWQtb2ZmLWJ5OiBDaHJpcyBXaWxzb24gPGNocmlzQGNocmlzLXdpbHNv bi5jby51az4KPiBDYzogQWthc2ggR29lbCA8YWthc2guZ29lbEBpbnRlbC5jb20+Cj4gQ2M6IERh bmllbCBWZXR0ZXIgPGRhbmllbC52ZXR0ZXJAZmZ3bGwuY2g+Cj4gQ2M6IFR2cnRrbyBVcnN1bGlu IDx0dnJ0a28udXJzdWxpbkBsaW51eC5pbnRlbC5jb20+Cj4gVGVzdGVkLWJ5OiBNYXR0aSBIw6Rt w6Rsw6RpbmVuIDxjY3JAdG5zcC5vcmc+Cj4gQ2M6IHN0YWJsZUB2Z2VyLmtlcm5lbC5vcmcKPiAt LS0KPiAgZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9nZW1fZXhlY2J1ZmZlci5jIHwgMTAgKysr LS0tLS0tLQo+ICAxIGZpbGUgY2hhbmdlZCwgMyBpbnNlcnRpb25zKCspLCA3IGRlbGV0aW9ucygt KQo+Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfZ2VtX2V4ZWNidWZm ZXIuYyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfZ2VtX2V4ZWNidWZmZXIuYwo+IGluZGV4 IDY5OTMxNTMwNDc0OC4uNzU5NTdhZWY2MjE5IDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2Ry bS9pOTE1L2k5MTVfZ2VtX2V4ZWNidWZmZXIuYwo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1 L2k5MTVfZ2VtX2V4ZWNidWZmZXIuYwo+IEBAIC0xMDE2LDcgKzEwMTYsNiBAQCBpOTE1X2dlbV9l eGVjYnVmZmVyX21vdmVfdG9fZ3B1KHN0cnVjdCBkcm1faTkxNV9nZW1fcmVxdWVzdCAqcmVxLAo+ ICAJY29uc3QgdW5zaWduZWQgaW50IG90aGVyX3JpbmdzID0gZWJfb3RoZXJfZW5naW5lcyhyZXEp Owo+ICAJc3RydWN0IGk5MTVfdm1hICp2bWE7Cj4gIAl1aW50MzJfdCBmbHVzaF9kb21haW5zID0g MDsKCllvdSBkb24ndCBuZWVkIGZsdXNoX2RvbWFpbnMsIHdpdGggdGhpcyB2ZXJzaW9uLgoKPiAt CWJvb2wgZmx1c2hfY2hpcHNldCA9IGZhbHNlOwo+ICAJaW50IHJldDsKPiAgCj4gIAlsaXN0X2Zv cl9lYWNoX2VudHJ5KHZtYSwgdm1hcywgZXhlY19saXN0KSB7Cj4gQEAgLTEwMjksMTYgKzEwMjgs MTMgQEAgaTkxNV9nZW1fZXhlY2J1ZmZlcl9tb3ZlX3RvX2dwdShzdHJ1Y3QgZHJtX2k5MTVfZ2Vt X3JlcXVlc3QgKnJlcSwKPiAgCQl9Cj4gIAo+ICAJCWlmIChvYmotPmJhc2Uud3JpdGVfZG9tYWlu ICYgSTkxNV9HRU1fRE9NQUlOX0NQVSkKPiAtCQkJZmx1c2hfY2hpcHNldCB8PSBpOTE1X2dlbV9j bGZsdXNoX29iamVjdChvYmosIGZhbHNlKTsKPiArCQkJaTkxNV9nZW1fY2xmbHVzaF9vYmplY3Qo b2JqLCBmYWxzZSk7Cj4gIAo+ICAJCWZsdXNoX2RvbWFpbnMgfD0gb2JqLT5iYXNlLndyaXRlX2Rv bWFpbjsKPiAgCX0KPiAgCj4gLQlpZiAoZmx1c2hfY2hpcHNldCkKPiAtCQlpOTE1X2dlbV9jaGlw c2V0X2ZsdXNoKHJlcS0+ZW5naW5lLT5pOTE1KTsKPiAtCj4gLQlpZiAoZmx1c2hfZG9tYWlucyAm IEk5MTVfR0VNX0RPTUFJTl9HVFQpCj4gLQkJd21iKCk7Cj4gKwkvKiBVbmNvbmRpdGlvbmFsbHkg Zmx1c2ggYW55IGNoaXBzZXQgY2FjaGVzIChmb3Igc3RyZWFtaW5nIHdyaXRlcykuICovCj4gKwlp OTE1X2dlbV9jaGlwc2V0X2ZsdXNoKHJlcS0+ZW5naW5lLT5pOTE1KTsKPiAgCj4gIAkvKiBVbmNv bmRpdGlvbmFsbHkgaW52YWxpZGF0ZSBHUFUgY2FjaGVzIGFuZCBUTEJzLiAqLwo+ICAJcmV0dXJu IHJlcS0+ZW5naW5lLT5lbWl0X2ZsdXNoKHJlcSwgRU1JVF9JTlZBTElEQVRFKTsKPiAtLSAKPiAy LjguMQo+Cj4gX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18K PiBJbnRlbC1nZnggbWFpbGluZyBsaXN0Cj4gSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9y Zwo+IGh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwt Z2Z4Cl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCkludGVs LWdmeCBtYWlsaW5nIGxpc3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczov L2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVsLWdmeAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com ([192.55.52.115]:40552 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752223AbcHPODK (ORCPT ); Tue, 16 Aug 2016 10:03:10 -0400 From: Mika Kuoppala To: Chris Wilson , intel-gfx@lists.freedesktop.org Cc: Daniel Vetter , Akash Goel , stable@vger.kernel.org Subject: Re: [Intel-gfx] [PATCH] drm/i915: Unconditionally flush any chipset buffers before execbuf In-Reply-To: <1471349672-9645-1-git-send-email-chris@chris-wilson.co.uk> References: <1471349672-9645-1-git-send-email-chris@chris-wilson.co.uk> Date: Tue, 16 Aug 2016 17:01:51 +0300 Message-ID: <87k2fgolrk.fsf@gaia.fi.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Sender: stable-owner@vger.kernel.org List-ID: Chris Wilson writes: > If userspace is asynchronously streaming into the batch or other > execobjects, we may not flush those writes along with a change in cache > domain (as there is no change). Therefore those writes may end up in > internal chipset buffers and not visible to the GPU upon execution. We > must issue a flush command or otherwise we encounter incoherency in the > batchbuffers and the GPU executing invalid commands (i.e. hanging) quite > regularly. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90841 > Fixes: 1816f9236303 ("drm/i915: Support creation of unbound wc user...") > Signed-off-by: Chris Wilson > Cc: Akash Goel > Cc: Daniel Vetter > Cc: Tvrtko Ursulin > Tested-by: Matti Hämäläinen > Cc: stable@vger.kernel.org > --- > drivers/gpu/drm/i915/i915_gem_execbuffer.c | 10 +++------- > 1 file changed, 3 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > index 699315304748..75957aef6219 100644 > --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > @@ -1016,7 +1016,6 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req, > const unsigned int other_rings = eb_other_engines(req); > struct i915_vma *vma; > uint32_t flush_domains = 0; You don't need flush_domains, with this version. > - bool flush_chipset = false; > int ret; > > list_for_each_entry(vma, vmas, exec_list) { > @@ -1029,16 +1028,13 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req, > } > > if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) > - flush_chipset |= i915_gem_clflush_object(obj, false); > + i915_gem_clflush_object(obj, false); > > flush_domains |= obj->base.write_domain; > } > > - if (flush_chipset) > - i915_gem_chipset_flush(req->engine->i915); > - > - if (flush_domains & I915_GEM_DOMAIN_GTT) > - wmb(); > + /* Unconditionally flush any chipset caches (for streaming writes). */ > + i915_gem_chipset_flush(req->engine->i915); > > /* Unconditionally invalidate GPU caches and TLBs. */ > return req->engine->emit_flush(req, EMIT_INVALIDATE); > -- > 2.8.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx