From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mika Kuoppala Subject: Re: [PATCH] drm/i915/bdw: 3D_CHICKEN3 has write mask bits Date: Mon, 07 Jul 2014 16:06:02 +0300 Message-ID: <87k37puxmt.fsf@gaia.fi.intel.com> References: <1404733217-13185-1-git-send-email-michel.thierry@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id CC04E6E320 for ; Mon, 7 Jul 2014 06:06:45 -0700 (PDT) In-Reply-To: <1404733217-13185-1-git-send-email-michel.thierry@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: michel.thierry@intel.com, intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org michel.thierry@intel.com writes: > From: Michel Thierry > > The workaround to limit SDE poly depth FIFO to 2 is not applied because > 3D Chicken-3 mask bit is not set. > > WaLimitSizeOfSDEPolyFifo is only for BDW-A and could be removed. > > Signed-off-by: Michel Thierry Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/intel_pm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 31ae2b4..ae68df6 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5360,7 +5360,7 @@ static void gen8_init_clock_gating(struct drm_device *dev) > I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE)); > > I915_WRITE(_3D_CHICKEN3, > - _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)); > + _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2))); > > I915_WRITE(COMMON_SLICE_CHICKEN2, > _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE)); > -- > 1.9.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx