* [Qemu-devel] [PATCH 1/7] qtest: don't use system command to avoid double fork
2013-04-16 14:45 [Qemu-devel] [PATCH 0/7] qtest: add libqos Anthony Liguori
@ 2013-04-16 14:45 ` Anthony Liguori
2013-04-16 14:45 ` [Qemu-devel] [PATCH 2/7] qtest: add libqos including PCI support Anthony Liguori
` (6 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Anthony Liguori @ 2013-04-16 14:45 UTC (permalink / raw)
To: qemu-devel; +Cc: Anthony Liguori
Currently we waitpid on the child process we spawn off that does
nothing more than system() another process. While this does not
appear to be incorrect, it's wasteful and confusing so get rid of
it.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
---
tests/libqtest.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/tests/libqtest.c b/tests/libqtest.c
index 389596a..884f959 100644
--- a/tests/libqtest.c
+++ b/tests/libqtest.c
@@ -107,7 +107,7 @@ static pid_t qtest_qemu_pid(QTestState *s)
QTestState *qtest_init(const char *extra_args)
{
QTestState *s;
- int sock, qmpsock, ret, i;
+ int sock, qmpsock, i;
gchar *pid_file;
gchar *command;
const char *qemu_binary;
@@ -136,10 +136,8 @@ QTestState *qtest_init(const char *extra_args)
"%s", qemu_binary, s->socket_path,
s->qmp_socket_path, pid_file,
extra_args ?: "");
-
- ret = system(command);
- exit(ret);
- g_free(command);
+ execlp("/bin/sh", "sh", "-c", command, NULL);
+ exit(1);
}
s->fd = socket_accept(sock);
@@ -169,9 +167,8 @@ void qtest_quit(QTestState *s)
pid_t pid = qtest_qemu_pid(s);
if (pid != -1) {
- /* kill QEMU, but wait for the child created by us to run system() */
kill(pid, SIGTERM);
- waitpid(s->child_pid, &status, 0);
+ waitpid(pid, &status, 0);
}
unlink(s->pid_file);
--
1.8.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH 2/7] qtest: add libqos including PCI support
2013-04-16 14:45 [Qemu-devel] [PATCH 0/7] qtest: add libqos Anthony Liguori
2013-04-16 14:45 ` [Qemu-devel] [PATCH 1/7] qtest: don't use system command to avoid double fork Anthony Liguori
@ 2013-04-16 14:45 ` Anthony Liguori
2013-04-16 14:45 ` [Qemu-devel] [PATCH 3/7] libqos: add fw_cfg support Anthony Liguori
` (5 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Anthony Liguori @ 2013-04-16 14:45 UTC (permalink / raw)
To: qemu-devel; +Cc: Anthony Liguori
This includes basic PCI support for the PC platform. Enough
abstraction should be present to support non-PC platforms too.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
---
v1 -> v2
- fixup size calculation (Kevin Wolf)
---
configure | 2 +-
tests/Makefile | 5 +-
tests/libqos/pci-pc.c | 239 ++++++++++++++++++++++++++++++++++++++++++++++++++
tests/libqos/pci-pc.h | 20 +++++
tests/libqos/pci.c | 151 +++++++++++++++++++++++++++++++
tests/libqos/pci.h | 80 +++++++++++++++++
6 files changed, 495 insertions(+), 2 deletions(-)
create mode 100644 tests/libqos/pci-pc.c
create mode 100644 tests/libqos/pci-pc.h
create mode 100644 tests/libqos/pci.c
create mode 100644 tests/libqos/pci.h
diff --git a/configure b/configure
index 0788e27..d7484ad 100755
--- a/configure
+++ b/configure
@@ -4475,7 +4475,7 @@ if [ "$pixman" = "internal" ]; then
fi
# build tree in object directory in case the source is not in the current directory
-DIRS="tests tests/tcg tests/tcg/cris tests/tcg/lm32"
+DIRS="tests tests/tcg tests/tcg/cris tests/tcg/lm32 tests/libqos"
DIRS="$DIRS pc-bios/optionrom pc-bios/spapr-rtas"
DIRS="$DIRS roms/seabios roms/vgabios"
DIRS="$DIRS qapi-generated"
diff --git a/tests/Makefile b/tests/Makefile
index 7fa15c6..5303b29 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -77,6 +77,7 @@ test-obj-y = tests/check-qint.o tests/check-qstring.o tests/check-qdict.o \
test-qapi-obj-y = tests/test-qapi-visit.o tests/test-qapi-types.o
$(test-obj-y): QEMU_INCLUDES += -Itests
+QEMU_CFLAGS += -I$(SRC_PATH)/tests
tests/test-x86-cpuid.o: QEMU_INCLUDES += -I$(SRC_PATH)/target-i386
@@ -105,7 +106,6 @@ tests/test-qmp-commands.h tests/test-qmp-marshal.c :\
$(SRC_PATH)/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-commands.py
$(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-commands.py $(gen-out-type) -o tests -p "test-" < $<, " GEN $@")
-
tests/test-string-output-visitor$(EXESUF): tests/test-string-output-visitor.o $(test-qapi-obj-y) libqemuutil.a libqemustub.a
tests/test-string-input-visitor$(EXESUF): tests/test-string-input-visitor.o $(test-qapi-obj-y) libqemuutil.a libqemustub.a
tests/test-qmp-output-visitor$(EXESUF): tests/test-qmp-output-visitor.o $(test-qapi-obj-y) libqemuutil.a libqemustub.a
@@ -116,6 +116,9 @@ tests/test-visitor-serialization$(EXESUF): tests/test-visitor-serialization.o $(
tests/test-mul64$(EXESUF): tests/test-mul64.o libqemuutil.a
+libqos-obj-y = tests/libqos/pci.o
+libqos-pc-obj-y = $(libqos-obj-y) tests/libqos/pci-pc.o
+
tests/rtc-test$(EXESUF): tests/rtc-test.o
tests/m48t59-test$(EXESUF): tests/m48t59-test.o
tests/fdc-test$(EXESUF): tests/fdc-test.o
diff --git a/tests/libqos/pci-pc.c b/tests/libqos/pci-pc.c
new file mode 100644
index 0000000..3bde8ab
--- /dev/null
+++ b/tests/libqos/pci-pc.c
@@ -0,0 +1,239 @@
+/*
+ * libqos PCI bindings for PC
+ *
+ * Copyright IBM, Corp. 2012-2013
+ *
+ * Authors:
+ * Anthony Liguori <aliguori@us.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "libqtest.h"
+#include "libqos/pci-pc.h"
+
+#include "hw/pci/pci_regs.h"
+
+#include "qemu-common.h"
+#include "qemu/host-utils.h"
+
+#include <glib.h>
+
+typedef struct QPCIBusPC
+{
+ QPCIBus bus;
+
+ uint32_t pci_hole_start;
+ uint32_t pci_hole_size;
+ uint32_t pci_hole_alloc;
+
+ uint16_t pci_iohole_start;
+ uint16_t pci_iohole_size;
+ uint16_t pci_iohole_alloc;
+} QPCIBusPC;
+
+static uint8_t qpci_pc_io_readb(QPCIBus *bus, void *addr)
+{
+ uintptr_t port = (uintptr_t)addr;
+ uint8_t value;
+
+ if (port < 0x10000) {
+ value = inb(port);
+ } else {
+ memread(port, &value, sizeof(value));
+ }
+
+ return value;
+}
+
+static uint16_t qpci_pc_io_readw(QPCIBus *bus, void *addr)
+{
+ uintptr_t port = (uintptr_t)addr;
+ uint16_t value;
+
+ if (port < 0x10000) {
+ value = inw(port);
+ } else {
+ memread(port, &value, sizeof(value));
+ }
+
+ return value;
+}
+
+static uint32_t qpci_pc_io_readl(QPCIBus *bus, void *addr)
+{
+ uintptr_t port = (uintptr_t)addr;
+ uint32_t value;
+
+ if (port < 0x10000) {
+ value = inl(port);
+ } else {
+ memread(port, &value, sizeof(value));
+ }
+
+ return value;
+}
+
+static void qpci_pc_io_writeb(QPCIBus *bus, void *addr, uint8_t value)
+{
+ uintptr_t port = (uintptr_t)addr;
+
+ if (port < 0x10000) {
+ outb(port, value);
+ } else {
+ memwrite(port, &value, sizeof(value));
+ }
+}
+
+static void qpci_pc_io_writew(QPCIBus *bus, void *addr, uint16_t value)
+{
+ uintptr_t port = (uintptr_t)addr;
+
+ if (port < 0x10000) {
+ outw(port, value);
+ } else {
+ memwrite(port, &value, sizeof(value));
+ }
+}
+
+static void qpci_pc_io_writel(QPCIBus *bus, void *addr, uint32_t value)
+{
+ uintptr_t port = (uintptr_t)addr;
+
+ if (port < 0x10000) {
+ outl(port, value);
+ } else {
+ memwrite(port, &value, sizeof(value));
+ }
+}
+
+static uint8_t qpci_pc_config_readb(QPCIBus *bus, int devfn, uint8_t offset)
+{
+ outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
+ return inb(0xcfc);
+}
+
+static uint16_t qpci_pc_config_readw(QPCIBus *bus, int devfn, uint8_t offset)
+{
+ outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
+ return inw(0xcfc);
+}
+
+static uint32_t qpci_pc_config_readl(QPCIBus *bus, int devfn, uint8_t offset)
+{
+ outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
+ return inl(0xcfc);
+}
+
+static void qpci_pc_config_writeb(QPCIBus *bus, int devfn, uint8_t offset, uint8_t value)
+{
+ outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
+ outb(0xcfc, value);
+}
+
+static void qpci_pc_config_writew(QPCIBus *bus, int devfn, uint8_t offset, uint16_t value)
+{
+ outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
+ outw(0xcfc, value);
+}
+
+static void qpci_pc_config_writel(QPCIBus *bus, int devfn, uint8_t offset, uint32_t value)
+{
+ outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
+ outl(0xcfc, value);
+}
+
+static void *qpci_pc_iomap(QPCIBus *bus, QPCIDevice *dev, int barno)
+{
+ QPCIBusPC *s = container_of(bus, QPCIBusPC, bus);
+ static const int bar_reg_map[] = {
+ PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2,
+ PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5,
+ };
+ int bar_reg;
+ uint32_t addr;
+ uint64_t size;
+ uint32_t io_type;
+
+ g_assert(barno >= 0 && barno <= 5);
+ bar_reg = bar_reg_map[barno];
+
+ qpci_config_writel(dev, bar_reg, 0xFFFFFFFF);
+ addr = qpci_config_readl(dev, bar_reg);
+
+ io_type = addr & PCI_BASE_ADDRESS_SPACE;
+ if (io_type == PCI_BASE_ADDRESS_SPACE_IO) {
+ addr &= PCI_BASE_ADDRESS_IO_MASK;
+ } else {
+ addr &= PCI_BASE_ADDRESS_MEM_MASK;
+ }
+
+ size = (1ULL << ctzl(addr));
+ if (size == 0) {
+ return NULL;
+ }
+
+ if (io_type == PCI_BASE_ADDRESS_SPACE_IO) {
+ uint16_t loc;
+
+ g_assert((s->pci_iohole_alloc + size) <= s->pci_iohole_size);
+ loc = s->pci_iohole_start + s->pci_iohole_alloc;
+ s->pci_iohole_alloc += size;
+
+ qpci_config_writel(dev, bar_reg, loc | PCI_BASE_ADDRESS_SPACE_IO);
+
+ return (void *)(intptr_t)loc;
+ } else {
+ uint64_t loc;
+
+ g_assert((s->pci_hole_alloc + size) <= s->pci_hole_size);
+ loc = s->pci_hole_start + s->pci_hole_alloc;
+ s->pci_hole_alloc += size;
+
+ qpci_config_writel(dev, bar_reg, loc);
+
+ return (void *)(intptr_t)loc;
+ }
+}
+
+static void qpci_pc_iounmap(QPCIBus *bus, void *data)
+{
+ /* FIXME */
+}
+
+QPCIBus *qpci_init_pc(void)
+{
+ QPCIBusPC *ret;
+
+ ret = g_malloc(sizeof(*ret));
+
+ ret->bus.io_readb = qpci_pc_io_readb;
+ ret->bus.io_readw = qpci_pc_io_readw;
+ ret->bus.io_readl = qpci_pc_io_readl;
+
+ ret->bus.io_writeb = qpci_pc_io_writeb;
+ ret->bus.io_writew = qpci_pc_io_writew;
+ ret->bus.io_writel = qpci_pc_io_writel;
+
+ ret->bus.config_readb = qpci_pc_config_readb;
+ ret->bus.config_readw = qpci_pc_config_readw;
+ ret->bus.config_readl = qpci_pc_config_readl;
+
+ ret->bus.config_writeb = qpci_pc_config_writeb;
+ ret->bus.config_writew = qpci_pc_config_writew;
+ ret->bus.config_writel = qpci_pc_config_writel;
+
+ ret->bus.iomap = qpci_pc_iomap;
+ ret->bus.iounmap = qpci_pc_iounmap;
+
+ ret->pci_hole_start = 0xE0000000;
+ ret->pci_hole_size = 0x20000000;
+ ret->pci_hole_alloc = 0;
+
+ ret->pci_iohole_start = 0xc000;
+ ret->pci_iohole_size = 0x4000;
+ ret->pci_iohole_alloc = 0;
+
+ return &ret->bus;
+}
diff --git a/tests/libqos/pci-pc.h b/tests/libqos/pci-pc.h
new file mode 100644
index 0000000..4f7475f
--- /dev/null
+++ b/tests/libqos/pci-pc.h
@@ -0,0 +1,20 @@
+/*
+ * libqos PCI bindings for PC
+ *
+ * Copyright IBM, Corp. 2012-2013
+ *
+ * Authors:
+ * Anthony Liguori <aliguori@us.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef LIBQOS_PCI_PC_H
+#define LIBQOS_PCI_PC_H
+
+#include "libqos/pci.h"
+
+QPCIBus *qpci_init_pc(void);
+
+#endif
diff --git a/tests/libqos/pci.c b/tests/libqos/pci.c
new file mode 100644
index 0000000..95e287b
--- /dev/null
+++ b/tests/libqos/pci.c
@@ -0,0 +1,151 @@
+/*
+ * libqos PCI bindings
+ *
+ * Copyright IBM, Corp. 2012-2013
+ *
+ * Authors:
+ * Anthony Liguori <aliguori@us.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "libqos/pci.h"
+
+#include "hw/pci/pci_regs.h"
+#include <glib.h>
+
+#include <stdio.h>
+
+void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id,
+ void (*func)(QPCIDevice *dev, int devfn, void *data),
+ void *data)
+{
+ int slot;
+
+ for (slot = 0; slot < 32; slot++) {
+ int fn;
+
+ for (fn = 0; fn < 8; fn++) {
+ QPCIDevice *dev;
+
+ dev = qpci_device_find(bus, QPCI_DEVFN(slot, fn));
+ if (!dev) {
+ continue;
+ }
+
+ if (vendor_id != -1 &&
+ qpci_config_readw(dev, PCI_VENDOR_ID) != vendor_id) {
+ continue;
+ }
+
+ if (device_id != -1 &&
+ qpci_config_readw(dev, PCI_DEVICE_ID) != device_id) {
+ continue;
+ }
+
+ func(dev, QPCI_DEVFN(slot, fn), data);
+ }
+ }
+}
+
+QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn)
+{
+ QPCIDevice *dev;
+
+ dev = g_malloc0(sizeof(*dev));
+ dev->bus = bus;
+ dev->devfn = devfn;
+
+ if (qpci_config_readw(dev, PCI_VENDOR_ID) == 0xFFFF) {
+ g_free(dev);
+ return NULL;
+ }
+
+ return dev;
+}
+
+void qpci_device_enable(QPCIDevice *dev)
+{
+ uint16_t cmd;
+
+ /* FIXME -- does this need to be a bus callout? */
+ cmd = qpci_config_readw(dev, PCI_COMMAND);
+ cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
+ qpci_config_writew(dev, PCI_COMMAND, cmd);
+}
+
+uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset)
+{
+ return dev->bus->config_readb(dev->bus, dev->devfn, offset);
+}
+
+uint16_t qpci_config_readw(QPCIDevice *dev, uint8_t offset)
+{
+ return dev->bus->config_readw(dev->bus, dev->devfn, offset);
+}
+
+uint32_t qpci_config_readl(QPCIDevice *dev, uint8_t offset)
+{
+ return dev->bus->config_readl(dev->bus, dev->devfn, offset);
+}
+
+
+void qpci_config_writeb(QPCIDevice *dev, uint8_t offset, uint8_t value)
+{
+ dev->bus->config_writeb(dev->bus, dev->devfn, offset, value);
+}
+
+void qpci_config_writew(QPCIDevice *dev, uint8_t offset, uint16_t value)
+{
+ dev->bus->config_writew(dev->bus, dev->devfn, offset, value);
+}
+
+void qpci_config_writel(QPCIDevice *dev, uint8_t offset, uint32_t value)
+{
+ dev->bus->config_writew(dev->bus, dev->devfn, offset, value);
+}
+
+
+uint8_t qpci_io_readb(QPCIDevice *dev, void *data)
+{
+ return dev->bus->io_readb(dev->bus, data);
+}
+
+uint16_t qpci_io_readw(QPCIDevice *dev, void *data)
+{
+ return dev->bus->io_readw(dev->bus, data);
+}
+
+uint32_t qpci_io_readl(QPCIDevice *dev, void *data)
+{
+ return dev->bus->io_readl(dev->bus, data);
+}
+
+
+void qpci_io_writeb(QPCIDevice *dev, void *data, uint8_t value)
+{
+ dev->bus->io_writeb(dev->bus, data, value);
+}
+
+void qpci_io_writew(QPCIDevice *dev, void *data, uint16_t value)
+{
+ dev->bus->io_writew(dev->bus, data, value);
+}
+
+void qpci_io_writel(QPCIDevice *dev, void *data, uint32_t value)
+{
+ dev->bus->io_writel(dev->bus, data, value);
+}
+
+void *qpci_iomap(QPCIDevice *dev, int barno)
+{
+ return dev->bus->iomap(dev->bus, dev, barno);
+}
+
+void qpci_iounmap(QPCIDevice *dev, void *data)
+{
+ dev->bus->iounmap(dev->bus, data);
+}
+
+
diff --git a/tests/libqos/pci.h b/tests/libqos/pci.h
new file mode 100644
index 0000000..3439431
--- /dev/null
+++ b/tests/libqos/pci.h
@@ -0,0 +1,80 @@
+/*
+ * libqos PCI bindings
+ *
+ * Copyright IBM, Corp. 2012-2013
+ *
+ * Authors:
+ * Anthony Liguori <aliguori@us.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef LIBQOS_PCI_H
+#define LIBQOS_PCI_H
+
+#include <stdint.h>
+
+#define QPCI_DEVFN(dev, fn) (((dev) << 3) | (fn))
+
+typedef struct QPCIDevice QPCIDevice;
+typedef struct QPCIBus QPCIBus;
+
+struct QPCIBus
+{
+ uint8_t (*io_readb)(QPCIBus *bus, void *addr);
+ uint16_t (*io_readw)(QPCIBus *bus, void *addr);
+ uint32_t (*io_readl)(QPCIBus *bus, void *addr);
+
+ void (*io_writeb)(QPCIBus *bus, void *addr, uint8_t value);
+ void (*io_writew)(QPCIBus *bus, void *addr, uint16_t value);
+ void (*io_writel)(QPCIBus *bus, void *addr, uint32_t value);
+
+ uint8_t (*config_readb)(QPCIBus *bus, int devfn, uint8_t offset);
+ uint16_t (*config_readw)(QPCIBus *bus, int devfn, uint8_t offset);
+ uint32_t (*config_readl)(QPCIBus *bus, int devfn, uint8_t offset);
+
+ void (*config_writeb)(QPCIBus *bus, int devfn,
+ uint8_t offset, uint8_t value);
+ void (*config_writew)(QPCIBus *bus, int devfn,
+ uint8_t offset, uint16_t value);
+ void (*config_writel)(QPCIBus *bus, int devfn,
+ uint8_t offset, uint32_t value);
+
+ void *(*iomap)(QPCIBus *bus, QPCIDevice *dev, int barno);
+ void (*iounmap)(QPCIBus *bus, void *data);
+};
+
+struct QPCIDevice
+{
+ QPCIBus *bus;
+ int devfn;
+};
+
+void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id,
+ void (*func)(QPCIDevice *dev, int devfn, void *data),
+ void *data);
+QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn);
+
+void qpci_device_enable(QPCIDevice *dev);
+
+uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset);
+uint16_t qpci_config_readw(QPCIDevice *dev, uint8_t offset);
+uint32_t qpci_config_readl(QPCIDevice *dev, uint8_t offset);
+
+void qpci_config_writeb(QPCIDevice *dev, uint8_t offset, uint8_t value);
+void qpci_config_writew(QPCIDevice *dev, uint8_t offset, uint16_t value);
+void qpci_config_writel(QPCIDevice *dev, uint8_t offset, uint32_t value);
+
+uint8_t qpci_io_readb(QPCIDevice *dev, void *data);
+uint16_t qpci_io_readw(QPCIDevice *dev, void *data);
+uint32_t qpci_io_readl(QPCIDevice *dev, void *data);
+
+void qpci_io_writeb(QPCIDevice *dev, void *data, uint8_t value);
+void qpci_io_writew(QPCIDevice *dev, void *data, uint16_t value);
+void qpci_io_writel(QPCIDevice *dev, void *data, uint32_t value);
+
+void *qpci_iomap(QPCIDevice *dev, int barno);
+void qpci_iounmap(QPCIDevice *dev, void *data);
+
+#endif
--
1.8.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH 3/7] libqos: add fw_cfg support
2013-04-16 14:45 [Qemu-devel] [PATCH 0/7] qtest: add libqos Anthony Liguori
2013-04-16 14:45 ` [Qemu-devel] [PATCH 1/7] qtest: don't use system command to avoid double fork Anthony Liguori
2013-04-16 14:45 ` [Qemu-devel] [PATCH 2/7] qtest: add libqos including PCI support Anthony Liguori
@ 2013-04-16 14:45 ` Anthony Liguori
2013-04-16 14:45 ` [Qemu-devel] [PATCH 4/7] libqos: add malloc support Anthony Liguori
` (4 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Anthony Liguori @ 2013-04-16 14:45 UTC (permalink / raw)
To: qemu-devel; +Cc: Anthony Liguori
fw_cfg is needed to get the top of memory which is necessary for
doing PCI allocation and allocating RAM for DMA.
Add a PC version of fw_cfg and enough abstraction to support other
platforms.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
---
tests/Makefile | 4 ++--
tests/libqos/fw_cfg-pc.c | 40 +++++++++++++++++++++++++++++++++++++
tests/libqos/fw_cfg-pc.h | 20 +++++++++++++++++++
tests/libqos/fw_cfg.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++++
tests/libqos/fw_cfg.h | 34 ++++++++++++++++++++++++++++++++
5 files changed, 147 insertions(+), 2 deletions(-)
create mode 100644 tests/libqos/fw_cfg-pc.c
create mode 100644 tests/libqos/fw_cfg-pc.h
create mode 100644 tests/libqos/fw_cfg.c
create mode 100644 tests/libqos/fw_cfg.h
diff --git a/tests/Makefile b/tests/Makefile
index 5303b29..ce91980 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -116,8 +116,8 @@ tests/test-visitor-serialization$(EXESUF): tests/test-visitor-serialization.o $(
tests/test-mul64$(EXESUF): tests/test-mul64.o libqemuutil.a
-libqos-obj-y = tests/libqos/pci.o
-libqos-pc-obj-y = $(libqos-obj-y) tests/libqos/pci-pc.o
+libqos-obj-y = tests/libqos/pci.o tests/libqos/fw_cfg.o
+libqos-pc-obj-y = $(libqos-obj-y) tests/libqos/pci-pc.o tests/libqos/fw_cfg-pc.o
tests/rtc-test$(EXESUF): tests/rtc-test.o
tests/m48t59-test$(EXESUF): tests/m48t59-test.o
diff --git a/tests/libqos/fw_cfg-pc.c b/tests/libqos/fw_cfg-pc.c
new file mode 100644
index 0000000..613604d
--- /dev/null
+++ b/tests/libqos/fw_cfg-pc.c
@@ -0,0 +1,40 @@
+/*
+ * libqos fw_cfg support for PC
+ *
+ * Copyright IBM, Corp. 2012-2013
+ *
+ * Authors:
+ * Anthony Liguori <aliguori@us.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "libqos/fw_cfg-pc.h"
+#include "libqtest.h"
+#include <glib.h>
+
+static void pc_fw_cfg_select(QFWCFG *fw_cfg, uint16_t key)
+{
+ outw(0x510, key);
+}
+
+static void pc_fw_cfg_read(QFWCFG *fw_cfg, void *data, size_t len)
+{
+ uint8_t *ptr = data;
+ int i;
+
+ for (i = 0; i < len; i++) {
+ ptr[i] = inb(0x511);
+ }
+}
+
+QFWCFG *pc_fw_cfg_init(void)
+{
+ QFWCFG *fw_cfg = g_malloc0(sizeof(*fw_cfg));
+
+ fw_cfg->select = pc_fw_cfg_select;
+ fw_cfg->read = pc_fw_cfg_read;
+
+ return fw_cfg;
+}
diff --git a/tests/libqos/fw_cfg-pc.h b/tests/libqos/fw_cfg-pc.h
new file mode 100644
index 0000000..444bd79
--- /dev/null
+++ b/tests/libqos/fw_cfg-pc.h
@@ -0,0 +1,20 @@
+/*
+ * libqos fw_cfg support for PC
+ *
+ * Copyright IBM, Corp. 2012-2013
+ *
+ * Authors:
+ * Anthony Liguori <aliguori@us.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef LIBQOS_FW_CFG_PC_H
+#define LIBQOS_FW_CFG_PC_H
+
+#include "libqos/fw_cfg.h"
+
+QFWCFG *pc_fw_cfg_init(void);
+
+#endif
diff --git a/tests/libqos/fw_cfg.c b/tests/libqos/fw_cfg.c
new file mode 100644
index 0000000..799139e
--- /dev/null
+++ b/tests/libqos/fw_cfg.c
@@ -0,0 +1,51 @@
+/*
+ * libqos fw_cfg support
+ *
+ * Copyright IBM, Corp. 2012-2013
+ *
+ * Authors:
+ * Anthony Liguori <aliguori@us.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "libqos/fw_cfg.h"
+
+void qfw_cfg_select(QFWCFG *fw_cfg, uint16_t key)
+{
+ fw_cfg->select(fw_cfg, key);
+}
+
+void qfw_cfg_read_data(QFWCFG *fw_cfg, void *data, size_t len)
+{
+ fw_cfg->read(fw_cfg, data, len);
+}
+
+void qfw_cfg_get(QFWCFG *fw_cfg, uint16_t key, void *data, size_t len)
+{
+ qfw_cfg_select(fw_cfg, key);
+ qfw_cfg_read_data(fw_cfg, data, len);
+}
+
+uint16_t qfw_cfg_get_u16(QFWCFG *fw_cfg, uint16_t key)
+{
+ uint16_t value;
+ qfw_cfg_get(fw_cfg, key, &value, sizeof(value));
+ return value;
+}
+
+uint32_t qfw_cfg_get_u32(QFWCFG *fw_cfg, uint16_t key)
+{
+ uint32_t value;
+ qfw_cfg_get(fw_cfg, key, &value, sizeof(value));
+ return value;
+}
+
+uint64_t qfw_cfg_get_u64(QFWCFG *fw_cfg, uint16_t key)
+{
+ uint64_t value;
+ qfw_cfg_get(fw_cfg, key, &value, sizeof(value));
+ return value;
+}
+
diff --git a/tests/libqos/fw_cfg.h b/tests/libqos/fw_cfg.h
new file mode 100644
index 0000000..44fc42b
--- /dev/null
+++ b/tests/libqos/fw_cfg.h
@@ -0,0 +1,34 @@
+/*
+ * libqos fw_cfg support
+ *
+ * Copyright IBM, Corp. 2012-2013
+ *
+ * Authors:
+ * Anthony Liguori <aliguori@us.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef LIBQOS_FW_CFG_H
+#define LIBQOS_FW_CFG_H
+
+#include <stdint.h>
+#include <sys/types.h>
+
+typedef struct QFWCFG QFWCFG;
+
+struct QFWCFG
+{
+ void (*select)(QFWCFG *fw_cfg, uint16_t key);
+ void (*read)(QFWCFG *fw_cfg, void *data, size_t len);
+};
+
+void qfw_cfg_select(QFWCFG *fw_cfg, uint16_t key);
+void qfw_cfg_read_data(QFWCFG *fw_cfg, void *data, size_t len);
+void qfw_cfg_get(QFWCFG *fw_cfg, uint16_t key, void *data, size_t len);
+uint16_t qfw_cfg_get_u16(QFWCFG *fw_cfg, uint16_t key);
+uint32_t qfw_cfg_get_u32(QFWCFG *fw_cfg, uint16_t key);
+uint64_t qfw_cfg_get_u64(QFWCFG *fw_cfg, uint16_t key);
+
+#endif
--
1.8.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH 4/7] libqos: add malloc support
2013-04-16 14:45 [Qemu-devel] [PATCH 0/7] qtest: add libqos Anthony Liguori
` (2 preceding siblings ...)
2013-04-16 14:45 ` [Qemu-devel] [PATCH 3/7] libqos: add fw_cfg support Anthony Liguori
@ 2013-04-16 14:45 ` Anthony Liguori
2013-04-16 14:45 ` [Qemu-devel] [PATCH 5/7] i440fx-test: add test to compare default register values Anthony Liguori
` (3 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Anthony Liguori @ 2013-04-16 14:45 UTC (permalink / raw)
To: qemu-devel; +Cc: Anthony Liguori
This is a very simple allocator for the PC platform. It should
be possible to add backends for other platforms.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
---
tests/Makefile | 1 +
tests/libqos/malloc-pc.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++++
tests/libqos/malloc-pc.h | 20 ++++++++++++++
tests/libqos/malloc.h | 38 ++++++++++++++++++++++++++
4 files changed, 130 insertions(+)
create mode 100644 tests/libqos/malloc-pc.c
create mode 100644 tests/libqos/malloc-pc.h
create mode 100644 tests/libqos/malloc.h
diff --git a/tests/Makefile b/tests/Makefile
index ce91980..cafbb27 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -118,6 +118,7 @@ tests/test-mul64$(EXESUF): tests/test-mul64.o libqemuutil.a
libqos-obj-y = tests/libqos/pci.o tests/libqos/fw_cfg.o
libqos-pc-obj-y = $(libqos-obj-y) tests/libqos/pci-pc.o tests/libqos/fw_cfg-pc.o
+libqos-pc-obj-y += tests/libqos/malloc-pc.o
tests/rtc-test$(EXESUF): tests/rtc-test.o
tests/m48t59-test$(EXESUF): tests/m48t59-test.o
diff --git a/tests/libqos/malloc-pc.c b/tests/libqos/malloc-pc.c
new file mode 100644
index 0000000..adc36c4
--- /dev/null
+++ b/tests/libqos/malloc-pc.c
@@ -0,0 +1,71 @@
+/*
+ * libqos malloc support for PC
+ *
+ * Copyright IBM, Corp. 2012-2013
+ *
+ * Authors:
+ * Anthony Liguori <aliguori@us.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "libqos/malloc-pc.h"
+#include "libqos/fw_cfg-pc.h"
+
+#define NO_QEMU_PROTOS
+#include "hw/nvram/fw_cfg.h"
+
+#include "qemu-common.h"
+#include <glib.h>
+
+#define PAGE_SIZE (4096)
+
+typedef struct PCAlloc
+{
+ QGuestAllocator alloc;
+
+ uint64_t start;
+ uint64_t end;
+} PCAlloc;
+
+static uint64_t pc_alloc(QGuestAllocator *allocator, size_t size)
+{
+ PCAlloc *s = container_of(allocator, PCAlloc, alloc);
+ uint64_t addr;
+
+
+ size += (PAGE_SIZE - 1);
+ size &= PAGE_SIZE;
+
+ g_assert_cmpint((s->start + size), <=, s->end);
+
+ addr = s->start;
+ s->start += size;
+
+ return addr;
+}
+
+static void pc_free(QGuestAllocator *allocator, uint64_t addr)
+{
+}
+
+QGuestAllocator *pc_alloc_init(void)
+{
+ PCAlloc *s = g_malloc0(sizeof(*s));
+ uint64_t ram_size;
+ QFWCFG *fw_cfg = pc_fw_cfg_init();
+
+ s->alloc.alloc = pc_alloc;
+ s->alloc.free = pc_free;
+
+ ram_size = qfw_cfg_get_u64(fw_cfg, FW_CFG_RAM_SIZE);
+
+ /* Start at 1MB */
+ s->start = 1 << 20;
+
+ /* Respect PCI hole */
+ s->end = MIN(ram_size, 0xE0000000);
+
+ return &s->alloc;
+}
diff --git a/tests/libqos/malloc-pc.h b/tests/libqos/malloc-pc.h
new file mode 100644
index 0000000..ff964ab
--- /dev/null
+++ b/tests/libqos/malloc-pc.h
@@ -0,0 +1,20 @@
+/*
+ * libqos malloc support for PC
+ *
+ * Copyright IBM, Corp. 2012-2013
+ *
+ * Authors:
+ * Anthony Liguori <aliguori@us.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef LIBQOS_MALLOC_PC_H
+#define LIBQOS_MALLOC_PC_H
+
+#include "libqos/malloc.h"
+
+QGuestAllocator *pc_alloc_init(void);
+
+#endif
diff --git a/tests/libqos/malloc.h b/tests/libqos/malloc.h
new file mode 100644
index 0000000..46f6000
--- /dev/null
+++ b/tests/libqos/malloc.h
@@ -0,0 +1,38 @@
+/*
+ * libqos malloc support
+ *
+ * Copyright IBM, Corp. 2012-2013
+ *
+ * Authors:
+ * Anthony Liguori <aliguori@us.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef LIBQOS_MALLOC_H
+#define LIBQOS_MALLOC_H
+
+#include <stdint.h>
+#include <sys/types.h>
+
+typedef struct QGuestAllocator QGuestAllocator;
+
+struct QGuestAllocator
+{
+ uint64_t (*alloc)(QGuestAllocator *allocator, size_t size);
+ void (*free)(QGuestAllocator *allocator, uint64_t addr);
+};
+
+/* Always returns page aligned values */
+static inline uint64_t guest_alloc(QGuestAllocator *allocator, size_t size)
+{
+ return allocator->alloc(allocator, size);
+}
+
+static inline void guest_free(QGuestAllocator *allocator, uint64_t addr)
+{
+ allocator->alloc(allocator, addr);
+}
+
+#endif
--
1.8.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH 5/7] i440fx-test: add test to compare default register values
2013-04-16 14:45 [Qemu-devel] [PATCH 0/7] qtest: add libqos Anthony Liguori
` (3 preceding siblings ...)
2013-04-16 14:45 ` [Qemu-devel] [PATCH 4/7] libqos: add malloc support Anthony Liguori
@ 2013-04-16 14:45 ` Anthony Liguori
2013-04-16 15:56 ` Eric Blake
2013-04-16 14:45 ` [Qemu-devel] [PATCH 6/7] i440fx-test: add test for PAM functionality Anthony Liguori
` (2 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Anthony Liguori @ 2013-04-16 14:45 UTC (permalink / raw)
To: qemu-devel; +Cc: Anthony Liguori
This test compares all of the default register values against the
spec. It turns out we deviate in quite a few places. These
places are really only visible to the BIOS though which is why
this hasn't created any problems.
The deviation actually happens in the core PCI layer so I suspect
it's not a simple fix if we really care to fix it. For now, just
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
---
tests/Makefile | 2 +
tests/i440fx-test.c | 148 ++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 150 insertions(+)
create mode 100644 tests/i440fx-test.c
diff --git a/tests/Makefile b/tests/Makefile
index cafbb27..6c4b910 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -54,6 +54,7 @@ gcov-files-i386-y = hw/fdc.c
check-qtest-i386-y += tests/hd-geo-test$(EXESUF)
gcov-files-i386-y += hw/hd-geometry.c
check-qtest-i386-y += tests/rtc-test$(EXESUF)
+check-qtest-i386-y += tests/i440fx-test$(EXESUF)
check-qtest-x86_64-y = $(check-qtest-i386-y)
gcov-files-i386-y += i386-softmmu/hw/mc146818rtc.c
gcov-files-x86_64-y = $(subst i386-softmmu/,x86_64-softmmu/,$(gcov-files-i386-y))
@@ -125,6 +126,7 @@ tests/m48t59-test$(EXESUF): tests/m48t59-test.o
tests/fdc-test$(EXESUF): tests/fdc-test.o
tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o
tests/tmp105-test$(EXESUF): tests/tmp105-test.o
+tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y)
# QTest rules
diff --git a/tests/i440fx-test.c b/tests/i440fx-test.c
new file mode 100644
index 0000000..6fba741
--- /dev/null
+++ b/tests/i440fx-test.c
@@ -0,0 +1,148 @@
+/*
+ * qtest I440FX test case
+ *
+ * Copyright IBM, Corp. 2012-2013
+ *
+ * Authors:
+ * Anthony Liguori <aliguori@us.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "libqos/pci.h"
+#include "libqos/pci-pc.h"
+#include "libqtest.h"
+
+#include "hw/pci/pci_regs.h"
+
+#include <glib.h>
+#include <stdio.h>
+
+#define BROKEN 1
+
+typedef struct TestData
+{
+ int num_cpus;
+ QPCIBus *bus;
+} TestData;
+
+static void test_i440fx_defaults(gconstpointer opaque)
+{
+ const TestData *s = opaque;
+ QPCIDevice *dev;
+ uint32_t value;
+
+ dev = qpci_device_find(s->bus, QPCI_DEVFN(0, 0));
+ g_assert(dev != NULL);
+
+ /* 3.2.2 */
+ g_assert_cmpint(qpci_config_readw(dev, PCI_VENDOR_ID), ==, 0x8086);
+ /* 3.2.3 */
+ g_assert_cmpint(qpci_config_readw(dev, PCI_DEVICE_ID), ==, 0x1237);
+#ifndef BROKEN
+ /* 3.2.4 */
+ g_assert_cmpint(qpci_config_readw(dev, PCI_COMMAND), ==, 0x0006);
+ /* 3.2.5 */
+ g_assert_cmpint(qpci_config_readw(dev, PCI_STATUS), ==, 0x0280);
+#endif
+ /* 3.2.7 */
+ g_assert_cmpint(qpci_config_readb(dev, PCI_CLASS_PROG), ==, 0x00);
+ g_assert_cmpint(qpci_config_readw(dev, PCI_CLASS_DEVICE), ==, 0x0600);
+ /* 3.2.8 */
+ g_assert_cmpint(qpci_config_readb(dev, PCI_LATENCY_TIMER), ==, 0x00);
+ /* 3.2.9 */
+ g_assert_cmpint(qpci_config_readb(dev, PCI_HEADER_TYPE), ==, 0x00);
+ /* 3.2.10 */
+ g_assert_cmpint(qpci_config_readb(dev, PCI_BIST), ==, 0x00);
+
+ /* 3.2.11 */
+ value = qpci_config_readw(dev, 0x50); /* PMCCFG */
+ if (s->num_cpus == 1) { /* WPE */
+ g_assert(!(value & (1 << 15)));
+ } else {
+ g_assert((value & (1 << 15)));
+ }
+
+ g_assert(!(value & (1 << 6))); /* EPTE */
+
+ /* 3.2.12 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x52), ==, 0x00); /* DETURBO */
+ /* 3.2.13 */
+#ifndef BROKEN
+ g_assert_cmpint(qpci_config_readb(dev, 0x53), ==, 0x80); /* DBC */
+#endif
+ /* 3.2.14 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x54), ==, 0x00); /* AXC */
+ /* 3.2.15 */
+ g_assert_cmpint(qpci_config_readw(dev, 0x55), ==, 0x0000); /* DRT */
+#ifndef BROKEN
+ /* 3.2.16 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x57), ==, 0x01); /* DRAMC */
+ /* 3.2.17 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x58), ==, 0x10); /* DRAMT */
+#endif
+ /* 3.2.18 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x59), ==, 0x00); /* PAM0 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x5A), ==, 0x00); /* PAM1 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x5B), ==, 0x00); /* PAM2 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x5C), ==, 0x00); /* PAM3 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x5D), ==, 0x00); /* PAM4 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x5E), ==, 0x00); /* PAM5 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x5F), ==, 0x00); /* PAM6 */
+#ifndef BROKEN
+ /* 3.2.19 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x60), ==, 0x01); /* DRB0 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x61), ==, 0x01); /* DRB1 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x62), ==, 0x01); /* DRB2 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x63), ==, 0x01); /* DRB3 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x64), ==, 0x01); /* DRB4 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x65), ==, 0x01); /* DRB5 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x66), ==, 0x01); /* DRB6 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x67), ==, 0x01); /* DRB7 */
+#endif
+ /* 3.2.20 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x68), ==, 0x00); /* FDHC */
+ /* 3.2.21 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x70), ==, 0x00); /* MTT */
+#ifndef BROKEN
+ /* 3.2.22 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x71), ==, 0x10); /* CLT */
+#endif
+ /* 3.2.23 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x72), ==, 0x02); /* SMRAM */
+ /* 3.2.24 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x90), ==, 0x00); /* ERRCMD */
+ /* 3.2.25 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x91), ==, 0x00); /* ERRSTS */
+ /* 3.2.26 */
+ g_assert_cmpint(qpci_config_readb(dev, 0x93), ==, 0x00); /* TRC */
+}
+
+int main(int argc, char **argv)
+{
+ QTestState *s;
+ TestData data;
+ char *cmdline;
+ int ret;
+
+ g_test_init(&argc, &argv, NULL);
+
+ data.num_cpus = 1;
+
+ cmdline = g_strdup_printf("-display none -smp %d", data.num_cpus);
+ s = qtest_start(cmdline);
+ g_free(cmdline);
+
+ data.bus = qpci_init_pc();
+
+ g_test_add_data_func("/i440fx/defaults", &data, test_i440fx_defaults);
+
+ ret = g_test_run();
+
+ if (s) {
+ qtest_quit(s);
+ }
+
+ return ret;
+}
--
1.8.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PATCH 5/7] i440fx-test: add test to compare default register values
2013-04-16 14:45 ` [Qemu-devel] [PATCH 5/7] i440fx-test: add test to compare default register values Anthony Liguori
@ 2013-04-16 15:56 ` Eric Blake
2013-04-16 15:59 ` Eric Blake
0 siblings, 1 reply; 13+ messages in thread
From: Eric Blake @ 2013-04-16 15:56 UTC (permalink / raw)
To: Anthony Liguori; +Cc: qemu-devel
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On 04/16/2013 08:45 AM, Anthony Liguori wrote:
> This test compares all of the default register values against the
> spec. It turns out we deviate in quite a few places. These
> places are really only visible to the BIOS though which is why
> this hasn't created any problems.
>
> The deviation actually happens in the core PCI layer so I suspect
> it's not a simple fix if we really care to fix it. For now, just
>
Conclusion of sentence?
> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
> ---
> tests/Makefile | 2 +
> tests/i440fx-test.c | 148 ++++++++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 150 insertions(+)
> create mode 100644 tests/i440fx-test.c
>
--
Eric Blake eblake redhat com +1-919-301-3266
Libvirt virtualization library http://libvirt.org
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH 5/7] i440fx-test: add test to compare default register values
2013-04-16 15:56 ` Eric Blake
@ 2013-04-16 15:59 ` Eric Blake
2013-04-16 18:13 ` Anthony Liguori
0 siblings, 1 reply; 13+ messages in thread
From: Eric Blake @ 2013-04-16 15:59 UTC (permalink / raw)
Cc: Anthony Liguori, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 767 bytes --]
On 04/16/2013 09:56 AM, Eric Blake wrote:
> On 04/16/2013 08:45 AM, Anthony Liguori wrote:
>> This test compares all of the default register values against the
>> spec. It turns out we deviate in quite a few places. These
>> places are really only visible to the BIOS though which is why
>> this hasn't created any problems.
>>
>> The deviation actually happens in the core PCI layer so I suspect
>> it's not a simple fix if we really care to fix it. For now, just
>>
>
> Conclusion of sentence?
Probably a case of your wording being similar to '#if 0 out the broken
tests', and 'git commit' eating it because it looked like a comment.
--
Eric Blake eblake redhat com +1-919-301-3266
Libvirt virtualization library http://libvirt.org
[-- Attachment #2: OpenPGP digital signature --]
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH 5/7] i440fx-test: add test to compare default register values
2013-04-16 15:59 ` Eric Blake
@ 2013-04-16 18:13 ` Anthony Liguori
0 siblings, 0 replies; 13+ messages in thread
From: Anthony Liguori @ 2013-04-16 18:13 UTC (permalink / raw)
To: Eric Blake; +Cc: qemu-devel
Eric Blake <eblake@redhat.com> writes:
> On 04/16/2013 09:56 AM, Eric Blake wrote:
>> On 04/16/2013 08:45 AM, Anthony Liguori wrote:
>>> This test compares all of the default register values against the
>>> spec. It turns out we deviate in quite a few places. These
>>> places are really only visible to the BIOS though which is why
>>> this hasn't created any problems.
>>>
>>> The deviation actually happens in the core PCI layer so I suspect
>>> it's not a simple fix if we really care to fix it. For now, just
>>>
>>
>> Conclusion of sentence?
>
> Probably a case of your wording being similar to '#if 0 out the broken
> tests', and 'git commit' eating it because it looked like a comment.
Indeed :-/
Regards,
Anthony Liguori
>
> --
> Eric Blake eblake redhat com +1-919-301-3266
> Libvirt virtualization library http://libvirt.org
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH 6/7] i440fx-test: add test for PAM functionality
2013-04-16 14:45 [Qemu-devel] [PATCH 0/7] qtest: add libqos Anthony Liguori
` (4 preceding siblings ...)
2013-04-16 14:45 ` [Qemu-devel] [PATCH 5/7] i440fx-test: add test to compare default register values Anthony Liguori
@ 2013-04-16 14:45 ` Anthony Liguori
2013-04-16 14:45 ` [Qemu-devel] [PATCH 7/7] fw_cfg: add qtest test case Anthony Liguori
2013-04-22 18:35 ` [Qemu-devel] [PATCH 0/7] qtest: add libqos Anthony Liguori
7 siblings, 0 replies; 13+ messages in thread
From: Anthony Liguori @ 2013-04-16 14:45 UTC (permalink / raw)
To: qemu-devel; +Cc: Anthony Liguori
This tests PAM settings for the i440fx. This test does a lot of
byte MMIO which is fairly slow with qtest today. But the test
does complete in under 2 seconds.
We don't fully emulate PAM largely because of limitations with
KVM so we #if 0 that part of the test case.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
---
tests/i440fx-test.c | 139 +++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 138 insertions(+), 1 deletion(-)
diff --git a/tests/i440fx-test.c b/tests/i440fx-test.c
index 6fba741..08ce820 100644
--- a/tests/i440fx-test.c
+++ b/tests/i440fx-test.c
@@ -17,10 +17,12 @@
#include "hw/pci/pci_regs.h"
#include <glib.h>
-#include <stdio.h>
+#include <string.h>
#define BROKEN 1
+#define ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0]))
+
typedef struct TestData
{
int num_cpus;
@@ -119,6 +121,139 @@ static void test_i440fx_defaults(gconstpointer opaque)
g_assert_cmpint(qpci_config_readb(dev, 0x93), ==, 0x00); /* TRC */
}
+#define PAM_RE 1
+#define PAM_WE 2
+
+static void pam_set(QPCIDevice *dev, int index, int flags)
+{
+ int regno = 0x59 + (index / 2);
+ uint8_t reg;
+
+ reg = qpci_config_readb(dev, regno);
+ if (index & 1) {
+ reg = (reg & 0x0F) | (flags << 4);
+ } else {
+ reg = (reg & 0xF0) | flags;
+ }
+ qpci_config_writeb(dev, regno, reg);
+}
+
+static gboolean verify_area(uint32_t start, uint32_t end, uint8_t value)
+{
+ uint32_t size = end - start + 1;
+ gboolean ret = TRUE;
+ uint8_t *data;
+ int i;
+
+ data = g_malloc0(size);
+ memread(start, data, size);
+
+ g_test_message("verify_area: data[0] = 0x%x", data[0]);
+
+ for (i = 0; i < size; i++) {
+ if (data[i] != value) {
+ ret = FALSE;
+ break;
+ }
+ }
+
+ g_free(data);
+
+ return ret;
+}
+
+static void write_area(uint32_t start, uint32_t end, uint8_t value)
+{
+ uint32_t size = end - start + 1;
+ uint8_t *data;
+
+ data = g_malloc0(size);
+ memset(data, value, size);
+ memwrite(start, data, size);
+
+ g_free(data);
+}
+
+static void test_i440fx_pam(gconstpointer opaque)
+{
+ const TestData *s = opaque;
+ QPCIDevice *dev;
+ int i;
+ static struct {
+ uint32_t start;
+ uint32_t end;
+ } pam_area[] = {
+ { 0, 0 }, /* Reserved */
+ { 0xF0000, 0xFFFFF }, /* BIOS Area */
+ { 0xC0000, 0xC3FFF }, /* Option ROM */
+ { 0xC4000, 0xC7FFF }, /* Option ROM */
+ { 0xC8000, 0xCBFFF }, /* Option ROM */
+ { 0xCC000, 0xCFFFF }, /* Option ROM */
+ { 0xD0000, 0xD3FFF }, /* Option ROM */
+ { 0xD4000, 0xD7FFF }, /* Option ROM */
+ { 0xD8000, 0xDBFFF }, /* Option ROM */
+ { 0xDC000, 0xDFFFF }, /* Option ROM */
+ { 0xE0000, 0xE3FFF }, /* BIOS Extension */
+ { 0xE4000, 0xE7FFF }, /* BIOS Extension */
+ { 0xE8000, 0xEBFFF }, /* BIOS Extension */
+ { 0xEC000, 0xEFFFF }, /* BIOS Extension */
+ };
+
+ dev = qpci_device_find(s->bus, QPCI_DEVFN(0, 0));
+ g_assert(dev != NULL);
+
+ for (i = 0; i < ARRAY_SIZE(pam_area); i++) {
+ if (pam_area[i].start == pam_area[i].end) {
+ continue;
+ }
+
+ g_test_message("Checking area 0x%05x..0x%05x",
+ pam_area[i].start, pam_area[i].end);
+ /* Switch to RE for the area */
+ pam_set(dev, i, PAM_RE);
+ /* Verify the RAM is all zeros */
+ g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0));
+
+ /* Switch to WE for the area */
+ pam_set(dev, i, PAM_RE | PAM_WE);
+ /* Write out a non-zero mask to the full area */
+ write_area(pam_area[i].start, pam_area[i].end, 0x42);
+
+#ifndef BROKEN
+ /* QEMU only supports a limited form of PAM */
+
+ /* Switch to !RE for the area */
+ pam_set(dev, i, PAM_WE);
+ /* Verify the area is not our mask */
+ g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x42));
+#endif
+
+ /* Verify the area is our new mask */
+ g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x42));
+
+ /* Write out a new mask */
+ write_area(pam_area[i].start, pam_area[i].end, 0x82);
+
+#ifndef BROKEN
+ /* QEMU only supports a limited form of PAM */
+
+ /* Verify the area is not our mask */
+ g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));
+
+ /* Switch to RE for the area */
+ pam_set(dev, i, PAM_RE | PAM_WE);
+#endif
+ /* Verify the area is our new mask */
+ g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x82));
+
+ /* Reset area */
+ pam_set(dev, i, 0);
+
+ /* Verify the area is not our new mask */
+ g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));
+ }
+}
+
int main(int argc, char **argv)
{
QTestState *s;
@@ -137,6 +272,8 @@ int main(int argc, char **argv)
data.bus = qpci_init_pc();
g_test_add_data_func("/i440fx/defaults", &data, test_i440fx_defaults);
+ g_test_add_data_func("/i440fx/pam", &data, test_i440fx_pam);
+
ret = g_test_run();
--
1.8.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH 7/7] fw_cfg: add qtest test case
2013-04-16 14:45 [Qemu-devel] [PATCH 0/7] qtest: add libqos Anthony Liguori
` (5 preceding siblings ...)
2013-04-16 14:45 ` [Qemu-devel] [PATCH 6/7] i440fx-test: add test for PAM functionality Anthony Liguori
@ 2013-04-16 14:45 ` Anthony Liguori
2013-04-28 15:29 ` Andreas Färber
2013-04-22 18:35 ` [Qemu-devel] [PATCH 0/7] qtest: add libqos Anthony Liguori
7 siblings, 1 reply; 13+ messages in thread
From: Anthony Liguori @ 2013-04-16 14:45 UTC (permalink / raw)
To: qemu-devel; +Cc: Anthony Liguori
This validates some basic characteristics of fw_cfg.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
---
tests/Makefile | 2 +
tests/fw_cfg-test.c | 141 ++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 143 insertions(+)
create mode 100644 tests/fw_cfg-test.c
diff --git a/tests/Makefile b/tests/Makefile
index 6c4b910..72bf2cd 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -55,6 +55,7 @@ check-qtest-i386-y += tests/hd-geo-test$(EXESUF)
gcov-files-i386-y += hw/hd-geometry.c
check-qtest-i386-y += tests/rtc-test$(EXESUF)
check-qtest-i386-y += tests/i440fx-test$(EXESUF)
+check-qtest-i386-y += tests/fw_cfg-test$(EXESUF)
check-qtest-x86_64-y = $(check-qtest-i386-y)
gcov-files-i386-y += i386-softmmu/hw/mc146818rtc.c
gcov-files-x86_64-y = $(subst i386-softmmu/,x86_64-softmmu/,$(gcov-files-i386-y))
@@ -127,6 +128,7 @@ tests/fdc-test$(EXESUF): tests/fdc-test.o
tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o
tests/tmp105-test$(EXESUF): tests/tmp105-test.o
tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y)
+tests/fw_cfg-test$(EXESUF): tests/fw_cfg-test.o $(libqos-pc-obj-y)
# QTest rules
diff --git a/tests/fw_cfg-test.c b/tests/fw_cfg-test.c
new file mode 100644
index 0000000..c284c4d
--- /dev/null
+++ b/tests/fw_cfg-test.c
@@ -0,0 +1,141 @@
+/*
+ * qtest fw_cfg test case
+ *
+ * Copyright IBM, Corp. 2012-2013
+ *
+ * Authors:
+ * Anthony Liguori <aliguori@us.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#define NO_QEMU_PROTOS
+
+#include "libqtest.h"
+#include "hw/nvram/fw_cfg.h"
+#include "libqos/fw_cfg-pc.h"
+
+#include <string.h>
+#include <glib.h>
+
+static uint64_t ram_size = 128 << 20;
+static uint16_t nb_cpus = 1;
+static uint16_t max_cpus = 1;
+static uint64_t nb_nodes = 0;
+static uint16_t boot_menu = 0;
+static QFWCFG *fw_cfg = NULL;
+
+static void test_fw_cfg_signature(void)
+{
+ char buf[5];
+
+ qfw_cfg_get(fw_cfg, FW_CFG_SIGNATURE, buf, 4);
+ buf[4] = 0;
+
+ g_assert_cmpstr(buf, ==, "QEMU");
+}
+
+static void test_fw_cfg_id(void)
+{
+ g_assert_cmpint(qfw_cfg_get_u32(fw_cfg, FW_CFG_ID), ==, 1);
+}
+
+static void test_fw_cfg_uuid(void)
+{
+ uint8_t buf[16];
+ static const uint8_t uuid[16] = {
+ 0x46, 0x00, 0xcb, 0x32, 0x38, 0xec, 0x4b, 0x2f,
+ 0x8a, 0xcb, 0x81, 0xc6, 0xea, 0x54, 0xf2, 0xd8,
+ };
+
+ qfw_cfg_get(fw_cfg, FW_CFG_UUID, buf, 16);
+ g_assert(memcmp(buf, uuid, sizeof(buf)) == 0);
+}
+
+static void test_fw_cfg_ram_size(void)
+{
+ g_assert_cmpint(qfw_cfg_get_u64(fw_cfg, FW_CFG_RAM_SIZE), ==, ram_size);
+}
+
+static void test_fw_cfg_nographic(void)
+{
+ g_assert_cmpint(qfw_cfg_get_u16(fw_cfg, FW_CFG_NOGRAPHIC), ==, 0);
+}
+
+static void test_fw_cfg_nb_cpus(void)
+{
+ g_assert_cmpint(qfw_cfg_get_u16(fw_cfg, FW_CFG_NB_CPUS), ==, nb_cpus);
+}
+
+static void test_fw_cfg_max_cpus(void)
+{
+ g_assert_cmpint(qfw_cfg_get_u16(fw_cfg, FW_CFG_MAX_CPUS), ==, max_cpus);
+}
+
+static void test_fw_cfg_numa(void)
+{
+ uint64_t *cpu_mask;
+ uint64_t *node_mask;
+
+ g_assert_cmpint(qfw_cfg_get_u64(fw_cfg, FW_CFG_NUMA), ==, nb_nodes);
+
+ cpu_mask = g_malloc0(sizeof(uint64_t) * max_cpus);
+ node_mask = g_malloc0(sizeof(uint64_t) * nb_nodes);
+
+ qfw_cfg_read_data(fw_cfg, cpu_mask, sizeof(uint64_t) * max_cpus);
+ qfw_cfg_read_data(fw_cfg, node_mask, sizeof(uint64_t) * nb_nodes);
+
+ if (nb_nodes) {
+ g_assert(cpu_mask[0] & 0x01);
+ g_assert_cmpint(node_mask[0], ==, ram_size);
+ }
+
+ g_free(node_mask);
+ g_free(cpu_mask);
+}
+
+static void test_fw_cfg_boot_menu(void)
+{
+ g_assert_cmpint(qfw_cfg_get_u16(fw_cfg, FW_CFG_BOOT_MENU), ==, boot_menu);
+}
+
+int main(int argc, char **argv)
+{
+ QTestState *s;
+ char *cmdline;
+ int ret;
+
+ g_test_init(&argc, &argv, NULL);
+
+ fw_cfg = pc_fw_cfg_init();
+
+ g_test_add_func("/fw_cfg/signature", test_fw_cfg_signature);
+ g_test_add_func("/fw_cfg/id", test_fw_cfg_id);
+ g_test_add_func("/fw_cfg/uuid", test_fw_cfg_uuid);
+ g_test_add_func("/fw_cfg/ram_size", test_fw_cfg_ram_size);
+ g_test_add_func("/fw_cfg/nographic", test_fw_cfg_nographic);
+ g_test_add_func("/fw_cfg/nb_cpus", test_fw_cfg_nb_cpus);
+#if 0
+ g_test_add_func("/fw_cfg/machine_id", test_fw_cfg_machine_id);
+ g_test_add_func("/fw_cfg/kernel", test_fw_cfg_kernel);
+ g_test_add_func("/fw_cfg/initrd", test_fw_cfg_initrd);
+ g_test_add_func("/fw_cfg/boot_device", test_fw_cfg_boot_device);
+#endif
+ g_test_add_func("/fw_cfg/max_cpus", test_fw_cfg_max_cpus);
+ g_test_add_func("/fw_cfg/numa", test_fw_cfg_numa);
+ g_test_add_func("/fw_cfg/boot_menu", test_fw_cfg_boot_menu);
+
+ cmdline = g_strdup_printf("-display none "
+ "-uuid 4600cb32-38ec-4b2f-8acb-81c6ea54f2d8 ");
+ s = qtest_start(cmdline);
+ g_free(cmdline);
+
+ ret = g_test_run();
+
+ if (s) {
+ qtest_quit(s);
+ }
+
+ return ret;
+}
--
1.8.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PATCH 7/7] fw_cfg: add qtest test case
2013-04-16 14:45 ` [Qemu-devel] [PATCH 7/7] fw_cfg: add qtest test case Anthony Liguori
@ 2013-04-28 15:29 ` Andreas Färber
0 siblings, 0 replies; 13+ messages in thread
From: Andreas Färber @ 2013-04-28 15:29 UTC (permalink / raw)
To: Anthony Liguori; +Cc: qemu-ppc, qemu-devel, Alexander Graf
Am 16.04.2013 16:45, schrieb Anthony Liguori:
> This validates some basic characteristics of fw_cfg.
>
> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
> ---
> tests/Makefile | 2 +
> tests/fw_cfg-test.c | 141 ++++++++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 143 insertions(+)
> create mode 100644 tests/fw_cfg-test.c
[...]
> diff --git a/tests/fw_cfg-test.c b/tests/fw_cfg-test.c
> new file mode 100644
> index 0000000..c284c4d
> --- /dev/null
> +++ b/tests/fw_cfg-test.c
> @@ -0,0 +1,141 @@
> +/*
> + * qtest fw_cfg test case
> + *
> + * Copyright IBM, Corp. 2012-2013
> + *
> + * Authors:
> + * Anthony Liguori <aliguori@us.ibm.com>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + */
> +
> +#define NO_QEMU_PROTOS
> +
> +#include "libqtest.h"
> +#include "hw/nvram/fw_cfg.h"
> +#include "libqos/fw_cfg-pc.h"
> +
> +#include <string.h>
> +#include <glib.h>
> +
> +static uint64_t ram_size = 128 << 20;
> +static uint16_t nb_cpus = 1;
> +static uint16_t max_cpus = 1;
> +static uint64_t nb_nodes = 0;
> +static uint16_t boot_menu = 0;
> +static QFWCFG *fw_cfg = NULL;
> +
> +static void test_fw_cfg_signature(void)
> +{
> + char buf[5];
> +
> + qfw_cfg_get(fw_cfg, FW_CFG_SIGNATURE, buf, 4);
> + buf[4] = 0;
> +
> + g_assert_cmpstr(buf, ==, "QEMU");
> +}
> +
> +static void test_fw_cfg_id(void)
> +{
> + g_assert_cmpint(qfw_cfg_get_u32(fw_cfg, FW_CFG_ID), ==, 1);
Breaks on ppc:
GTESTER check-qtest-i386
main-loop: WARNING: I/O thread spun for 1000 iterations
main-loop: WARNING: I/O thread spun for 1000 iterations
main-loop: WARNING: I/O thread spun for 1000 iterations
**
ERROR:/home/andreas/QEMU/qemu/tests/fw_cfg-test.c:41:test_fw_cfg_id:
assertion failed (qfw_cfg_get_u32(fw_cfg, FW_CFG_ID) == 1): (16777216 == 1)
GTester: last random seed: R02Seb06159fdb5cae93a76e1fb2021712e6
**
ERROR:/home/andreas/QEMU/qemu/tests/fw_cfg-test.c:58:test_fw_cfg_ram_size:
assertion failed (qfw_cfg_get_u64(fw_cfg, FW_CFG_RAM_SIZE) == ram_size):
(34359738368 == 134217728)
GTester: last random seed: R02Sb790037de99dc72c4011de8746bcf891
**
ERROR:/home/andreas/QEMU/qemu/tests/fw_cfg-test.c:68:test_fw_cfg_nb_cpus: assertion
failed (qfw_cfg_get_u16(fw_cfg, FW_CFG_NB_CPUS) == nb_cpus): (256 == 1)
GTester: last random seed: R02S8cbc5ce02a292007de9990e752915719
**
ERROR:/home/andreas/QEMU/qemu/tests/fw_cfg-test.c:73:test_fw_cfg_max_cpus:
assertion failed (qfw_cfg_get_u16(fw_cfg, FW_CFG_MAX_CPUS) == max_cpus):
(256 == 1)
GTester: last random seed: R02S81c8abd06614ef0eef55cedea5f37429
make: *** [check-qtest-i386] Fehler 1
Andreas
> +}
> +
> +static void test_fw_cfg_uuid(void)
> +{
> + uint8_t buf[16];
> + static const uint8_t uuid[16] = {
> + 0x46, 0x00, 0xcb, 0x32, 0x38, 0xec, 0x4b, 0x2f,
> + 0x8a, 0xcb, 0x81, 0xc6, 0xea, 0x54, 0xf2, 0xd8,
> + };
> +
> + qfw_cfg_get(fw_cfg, FW_CFG_UUID, buf, 16);
> + g_assert(memcmp(buf, uuid, sizeof(buf)) == 0);
> +}
> +
> +static void test_fw_cfg_ram_size(void)
> +{
> + g_assert_cmpint(qfw_cfg_get_u64(fw_cfg, FW_CFG_RAM_SIZE), ==, ram_size);
> +}
> +
> +static void test_fw_cfg_nographic(void)
> +{
> + g_assert_cmpint(qfw_cfg_get_u16(fw_cfg, FW_CFG_NOGRAPHIC), ==, 0);
> +}
> +
> +static void test_fw_cfg_nb_cpus(void)
> +{
> + g_assert_cmpint(qfw_cfg_get_u16(fw_cfg, FW_CFG_NB_CPUS), ==, nb_cpus);
> +}
> +
> +static void test_fw_cfg_max_cpus(void)
> +{
> + g_assert_cmpint(qfw_cfg_get_u16(fw_cfg, FW_CFG_MAX_CPUS), ==, max_cpus);
> +}
> +
> +static void test_fw_cfg_numa(void)
> +{
> + uint64_t *cpu_mask;
> + uint64_t *node_mask;
> +
> + g_assert_cmpint(qfw_cfg_get_u64(fw_cfg, FW_CFG_NUMA), ==, nb_nodes);
> +
> + cpu_mask = g_malloc0(sizeof(uint64_t) * max_cpus);
> + node_mask = g_malloc0(sizeof(uint64_t) * nb_nodes);
> +
> + qfw_cfg_read_data(fw_cfg, cpu_mask, sizeof(uint64_t) * max_cpus);
> + qfw_cfg_read_data(fw_cfg, node_mask, sizeof(uint64_t) * nb_nodes);
> +
> + if (nb_nodes) {
> + g_assert(cpu_mask[0] & 0x01);
> + g_assert_cmpint(node_mask[0], ==, ram_size);
> + }
> +
> + g_free(node_mask);
> + g_free(cpu_mask);
> +}
> +
> +static void test_fw_cfg_boot_menu(void)
> +{
> + g_assert_cmpint(qfw_cfg_get_u16(fw_cfg, FW_CFG_BOOT_MENU), ==, boot_menu);
> +}
> +
> +int main(int argc, char **argv)
> +{
> + QTestState *s;
> + char *cmdline;
> + int ret;
> +
> + g_test_init(&argc, &argv, NULL);
> +
> + fw_cfg = pc_fw_cfg_init();
> +
> + g_test_add_func("/fw_cfg/signature", test_fw_cfg_signature);
> + g_test_add_func("/fw_cfg/id", test_fw_cfg_id);
> + g_test_add_func("/fw_cfg/uuid", test_fw_cfg_uuid);
> + g_test_add_func("/fw_cfg/ram_size", test_fw_cfg_ram_size);
> + g_test_add_func("/fw_cfg/nographic", test_fw_cfg_nographic);
> + g_test_add_func("/fw_cfg/nb_cpus", test_fw_cfg_nb_cpus);
> +#if 0
> + g_test_add_func("/fw_cfg/machine_id", test_fw_cfg_machine_id);
> + g_test_add_func("/fw_cfg/kernel", test_fw_cfg_kernel);
> + g_test_add_func("/fw_cfg/initrd", test_fw_cfg_initrd);
> + g_test_add_func("/fw_cfg/boot_device", test_fw_cfg_boot_device);
> +#endif
> + g_test_add_func("/fw_cfg/max_cpus", test_fw_cfg_max_cpus);
> + g_test_add_func("/fw_cfg/numa", test_fw_cfg_numa);
> + g_test_add_func("/fw_cfg/boot_menu", test_fw_cfg_boot_menu);
> +
> + cmdline = g_strdup_printf("-display none "
> + "-uuid 4600cb32-38ec-4b2f-8acb-81c6ea54f2d8 ");
> + s = qtest_start(cmdline);
> + g_free(cmdline);
> +
> + ret = g_test_run();
> +
> + if (s) {
> + qtest_quit(s);
> + }
> +
> + return ret;
> +}
>
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH 0/7] qtest: add libqos
2013-04-16 14:45 [Qemu-devel] [PATCH 0/7] qtest: add libqos Anthony Liguori
` (6 preceding siblings ...)
2013-04-16 14:45 ` [Qemu-devel] [PATCH 7/7] fw_cfg: add qtest test case Anthony Liguori
@ 2013-04-22 18:35 ` Anthony Liguori
7 siblings, 0 replies; 13+ messages in thread
From: Anthony Liguori @ 2013-04-22 18:35 UTC (permalink / raw)
To: Anthony Liguori, qemu-devel
Applied. Thanks.
Regards,
Anthony Liguori
^ permalink raw reply [flat|nested] 13+ messages in thread