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From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
To: Phileas Fogg <phileas-fogg@mail.ru>, Geoff Levand <geoff@infradead.org>,
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Phileas Fogg <phileas-fogg@mail.ru> writes:

>  And another note.
> I took a look at the MMU chapter in the Cell Architecture handbook and in=
deed the first 15 bits in VA are treated as 0 by the hardware.
>
> Quote:
>
> 1. High-order bits above 65 bits in the 80-bit virtual address (VA[0:14])=
 are not implemented. The hardware always
> =C2=A0=C2=A0 treats these bits as `0'. Software must not set these bits t=
o any other value than `0' or the results are undefined in
> =C2=A0=C2=A0 the PPE.
>
>

True, we missed the below part of ISA doc:

ISA doc says

"On implementations that support a virtual address size
of only n bits, n < 78, bits 0:77-n of the AVA field must be
zeros. "

The Cell document I found at=20

https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/7A77CCDF14FE70D58=
52575CA0074E8ED/$file/CellBE_Handbook_v1.12_3Apr09_pub.pdf

gives=20

Virtual Address (VA) Size -> 65 bits

So as per ISA, bits 0:12 should be zero, which should make 0:14 of PTE
fields zero for Cell.

I will try to do a patch.=20

Thanks for debugging this.

-aneesh