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autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 sashiko-bot@kernel.org writes: > Thank you for your contribution! Sashiko AI review found 1 potential issu= e(s) to consider: > - [High] drm/xe: 32-bit multiplication overflow in adjust_idledly() > -- > > commit 6274ddb08f811b772af3c2cc759b8be4b565872c > Author: Gustavo Sousa > > drm/xe: Use picosecond as common unit in adjust_idledly() > > This commit changes adjust_idledly() to use picoseconds instead of > nanoseconds as the common unit of time to avoid precision loss and > eliminate extra integer divisions. > >> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_h= w_engine.c >> index 6872d1ca656e2..dcc8a6d53c5d0 100644 >> --- a/drivers/gpu/drm/xe/xe_hw_engine.c >> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c >> @@ -585,17 +585,19 @@ static void hw_engine_init_early(struct xe_gt *gt,= struct xe_hw_engine *hwe, >> xe_reg_whitelist_process_engine(hwe); >> } >> =20 >> -static u32 idledly_floor_ticks(u32 idledly_ns, u32 idledly_units_ps) >> +static u32 idledly_floor_ticks(u64 idledly_ps, u32 idledly_units_ps) >> { >> - return DIV_ROUND_DOWN_ULL((u64)idledly_ns * 1000, idledly_units_ps); >> + return DIV_ROUND_DOWN_ULL(idledly_ps, idledly_units_ps); >> } >> =20 >> static void adjust_idledly(struct xe_hw_engine *hwe) >> { >> struct xe_gt *gt =3D hwe->gt; >> - u32 idledly, idledly_hw, idledly_reg_val, maxcnt; >> + u32 idledly_reg_val, maxcnt_reg_val; >> u32 idledly_units_ps =3D 8 * gt->info.timestamp_base; >> - u32 maxcnt_units_ns =3D 640; >> + u32 maxcnt_units_ps =3D 640000; >> + u64 idledly_ps, idledly_hw_ps; >> + u64 maxcnt_ps; >> bool inhibit_switch =3D false; >> bool wa_applied =3D false; >> bool clamped_below_maxcnt =3D false; >> @@ -604,29 +606,27 @@ static void adjust_idledly(struct xe_hw_engine *hw= e) >> return; >> =20 >> if (XE_GT_WA(gt, 16023105232) || XE_GT_WA(gt, 14025941587)) { >> - u32 mincnt_idledly_ns =3D 5000; >> + u32 mincnt_idledly_ps =3D 5000000; >> =20 >> /* xe_gt_clock_init() warns and zeroes timestamp_base on unknown crys= tal clock. */ >> if (!idledly_units_ps) >> return; >> =20 >> idledly_reg_val =3D xe_mmio_read32(>->mmio, RING_IDLEDLY(hwe->mmio_= base)); >> - maxcnt =3D xe_mmio_read32(>->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_bas= e)); >> - >> inhibit_switch =3D idledly_reg_val & INHIBIT_SWITCH_UNTIL_PREEMPTED; >> - idledly =3D REG_FIELD_GET(IDLE_DELAY, idledly_reg_val); >> - idledly =3D DIV_ROUND_CLOSEST_ULL((u64)idledly * idledly_units_ps, 10= 00); >> - idledly_hw =3D idledly; >> - maxcnt =3D REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt); >> - maxcnt *=3D maxcnt_units_ns; >> + idledly_ps =3D REG_FIELD_GET(IDLE_DELAY, idledly_reg_val) * idledly_u= nits_ps; >> + idledly_hw_ps =3D idledly_ps; >> + >> + maxcnt_reg_val =3D xe_mmio_read32(>->mmio, RING_PWRCTX_MAXCNT(hwe->= mmio_base)); >> + maxcnt_ps =3D REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt_reg_val) * maxcnt_= units_ps; > > [Severity: High] > Can the multiplications computing idledly_ps and maxcnt_ps in > adjust_idledly() overflow 32-bit unsigned arithmetic before being widened > to u64? > > In include/drm/intel/reg_bits.h, REG_FIELD_GET() returns a u32: > > #define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val)) > > Because idledly_units_ps and maxcnt_units_ps are both declared as u32, > both multiplications are evaluated in 32-bit arithmetic before assignment > to u64 idledly_ps and u64 maxcnt_ps. > > For idledly_ps, dropping the (u64) cast that was added in commit > d864065ea25e ("drm/xe: harden adjust_idledly() against divide-by-zero and > overflow") means IDLE_DELAY (a 21-bit field, REG_GENMASK(20, 0)) multipli= ed > by idledly_units_ps (up to 666,664 ps) wraps around U32_MAX whenever > IDLE_DELAY is >=3D 6443 ticks. > > Similarly, for maxcnt_ps, scaling the unit multiplier from 640 ns to > 640,000 ps in u32 means IDLE_WAIT_TIME (a 20-bit field, REG_GENMASK(19, 0= )) > multiplied by maxcnt_units_ps wraps around U32_MAX whenever IDLE_WAIT_TIM= E > is >=3D 6711 ticks (~4.29 ms out of its ~671 ms range). > > When either product wraps, xe_gt_WARN_ON(gt, idledly_hw_ps >=3D maxcnt_ps= ) > can trigger spuriously, and the Wa_14025941587 and Wa_16023105232 checks > can program a corrupted IDLE_DELAY tick count into RING_IDLEDLY. > > Should idledly_units_ps and maxcnt_units_ps be declared as u64 (or the > operands cast to u64 before multiplying)? Thanks for catching this. I'll make sure to add the cast to u64 to the operations in v2. -- Gustavo Sousa > > --=20 > Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20261023-wa_16031= 259911-v1-0-b0453f79c4e1@intel.com?part=3D3