Re: [PATCH v2 09/10] drm/xe: Enable all FORCE_TO_NONPRIV registers

["Dixit, Ashutosh" <ashutosh.dixit@intel.com>]

On Wed, 08 Apr 2026 16:43:08 -0700, Matt Roper wrote:
>

Hi Matt,

Wanted to pick up this patch, but doesn't look correct.

> Intel hardware supported by the Xe driver has 20 FORCE_TO_NONPRIV
> registers per engine.  We've only been enabling use of the first 12 so
> far because the upper 8 registers are not contiguous with the first 12.

Well the nonpriv register offsets are as follows (in hex):

	010 014 018 01C
	1E0 1E4 1E8 1EC
	4D0 4D4 4D8 4DC
	4E0 4E4 4E8 4EC
	4F0 4F4 4F8 4FC

So it is the upper 12 registers which are contiguous. And the lower 8
registers are not contiguous with the upper 12.

> Some upcoming changes are going to require more than 12 entries, so
> update the register definition to select the proper offset for all 20
> instances and allow them to all be used.
>
> Bspec: 60340
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_engine_regs.h | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> index 1b4a7e9a703d..d8f0915500ec 100644
> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> @@ -182,7 +182,10 @@
>  #define RING_CTX_TIMESTAMP_UDW(base)		XE_REG((base) + 0x3ac)
>  #define CSBE_DEBUG_STATUS(base)			XE_REG((base) + 0x3fc)
>
> -#define RING_FORCE_TO_NONPRIV(base, i)		XE_REG(((base) + 0x4d0) + (i) * 4)
> +#define RING_FORCE_TO_NONPRIV(base, i)          XE_REG((base) + \
> +						       _PICK_EVEN_2RANGES(i, 12, \
> +									  0x4d0, 0x4d4, \
> +									  0x010, 0x014))

Note that, from the nonpriv register offsets above, the lower 8 registers
are in *two* separate non-contiguous ranges. Therefore _PICK_EVEN_2RANGES()
does not work (if we are trying to include all 20 registers).

Thanks.
--
Ashutosh

>  #define   RING_FORCE_TO_NONPRIV_DENY		REG_BIT(30)
>  #define   RING_FORCE_TO_NONPRIV_ACCESS_MASK	REG_GENMASK(29, 28)
>  #define   RING_FORCE_TO_NONPRIV_ACCESS_RW	REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 0)
> @@ -198,7 +201,7 @@
>  #define   RING_FORCE_TO_NONPRIV_MASK_VALID	(RING_FORCE_TO_NONPRIV_RANGE_MASK | \
>						 RING_FORCE_TO_NONPRIV_ACCESS_MASK | \
>						 RING_FORCE_TO_NONPRIV_DENY)
> -#define   RING_MAX_NONPRIV_SLOTS  12
> +#define   RING_MAX_NONPRIV_SLOTS  20
>
>  #define RING_EXECLIST_SQ_CONTENTS_LO(base)	XE_REG((base) + 0x510)
>  #define RING_EXECLIST_SQ_CONTENTS_HI(base)	XE_REG((base) + 0x510 + 4)
>
> --
> 2.53.0
>