From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7B264CD6E57 for ; Tue, 2 Jun 2026 23:59:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 13A6010F6C0; Tue, 2 Jun 2026 23:59:00 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="DmFCIpsH"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4245310F6C0 for ; Tue, 2 Jun 2026 23:58:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780444738; x=1811980738; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=cGOTUaEBOKD1QZ5l2Cr8UHixQQDzljd47vEhNfDvzJA=; b=DmFCIpsH01YGzmgOQBlQ4iyj5eL4vIcSJ3igSetZgmd1k7uTH+HS6vlm /dvuZvfSbfPtnQc6xB4Q1PLkZGyHyyat+HkoSf8wtIorIS6a4iWUxuDLQ q7mpMyRoF73VTCkqyXeJDpQ0yCqAQ9vrWxFbpte1RaMi3l4qoNF3AR8L4 ErTIvodEVat2Y3PBYfUpxfKlONe2/H7kRddSeHaLALj000JmlDf7K74ZY UijvereLjL/UjQZzHHAGsRo2Kk6tQxO9ellA2E0iKmsnIOPlshtBc6z65 6A7nyjDL4YQvpsXWWJp+YAKwoGN6lor0c54qMS9zQDAUw0ZcMMcUJvrWH A==; X-CSE-ConnectionGUID: FUWqKeKzSgyIlSGwVhhx3A== X-CSE-MsgGUID: QYZRB4/sSxa7SYrF0XOtDA== X-IronPort-AV: E=McAfee;i="6800,10657,11805"; a="98807484" X-IronPort-AV: E=Sophos;i="6.24,184,1774335600"; d="scan'208";a="98807484" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2026 16:58:58 -0700 X-CSE-ConnectionGUID: fN5js+wqTIKTedF779PDAw== X-CSE-MsgGUID: PTqmvYyjRkKdJGBXAoi2IQ== X-ExtLoop1: 1 Received: from unknown (HELO adixit-MOBL3.intel.com) ([10.241.240.74]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2026 16:58:57 -0700 Date: Tue, 02 Jun 2026 16:58:57 -0700 Message-ID: <87ldcw7av2.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Matt Roper Cc: , Umesh Nerlige Ramappa Subject: Re: [PATCH v2 09/10] drm/xe: Enable all FORCE_TO_NONPRIV registers In-Reply-To: <20260408-oa-whitelist-cleanup-v2-9-db4a06aae8b0@intel.com> References: <20260408-oa-whitelist-cleanup-v2-0-db4a06aae8b0@intel.com> <20260408-oa-whitelist-cleanup-v2-9-db4a06aae8b0@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Wed, 08 Apr 2026 16:43:08 -0700, Matt Roper wrote: > Hi Matt, Wanted to pick up this patch, but doesn't look correct. > Intel hardware supported by the Xe driver has 20 FORCE_TO_NONPRIV > registers per engine. We've only been enabling use of the first 12 so > far because the upper 8 registers are not contiguous with the first 12. Well the nonpriv register offsets are as follows (in hex): 010 014 018 01C 1E0 1E4 1E8 1EC 4D0 4D4 4D8 4DC 4E0 4E4 4E8 4EC 4F0 4F4 4F8 4FC So it is the upper 12 registers which are contiguous. And the lower 8 registers are not contiguous with the upper 12. > Some upcoming changes are going to require more than 12 entries, so > update the register definition to select the proper offset for all 20 > instances and allow them to all be used. > > Bspec: 60340 > Signed-off-by: Matt Roper > --- > drivers/gpu/drm/xe/regs/xe_engine_regs.h | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h > index 1b4a7e9a703d..d8f0915500ec 100644 > --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h > +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h > @@ -182,7 +182,10 @@ > #define RING_CTX_TIMESTAMP_UDW(base) XE_REG((base) + 0x3ac) > #define CSBE_DEBUG_STATUS(base) XE_REG((base) + 0x3fc) > > -#define RING_FORCE_TO_NONPRIV(base, i) XE_REG(((base) + 0x4d0) + (i) * 4) > +#define RING_FORCE_TO_NONPRIV(base, i) XE_REG((base) + \ > + _PICK_EVEN_2RANGES(i, 12, \ > + 0x4d0, 0x4d4, \ > + 0x010, 0x014)) Note that, from the nonpriv register offsets above, the lower 8 registers are in *two* separate non-contiguous ranges. Therefore _PICK_EVEN_2RANGES() does not work (if we are trying to include all 20 registers). Thanks. -- Ashutosh > #define RING_FORCE_TO_NONPRIV_DENY REG_BIT(30) > #define RING_FORCE_TO_NONPRIV_ACCESS_MASK REG_GENMASK(29, 28) > #define RING_FORCE_TO_NONPRIV_ACCESS_RW REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 0) > @@ -198,7 +201,7 @@ > #define RING_FORCE_TO_NONPRIV_MASK_VALID (RING_FORCE_TO_NONPRIV_RANGE_MASK | \ > RING_FORCE_TO_NONPRIV_ACCESS_MASK | \ > RING_FORCE_TO_NONPRIV_DENY) > -#define RING_MAX_NONPRIV_SLOTS 12 > +#define RING_MAX_NONPRIV_SLOTS 20 > > #define RING_EXECLIST_SQ_CONTENTS_LO(base) XE_REG((base) + 0x510) > #define RING_EXECLIST_SQ_CONTENTS_HI(base) XE_REG((base) + 0x510 + 4) > > -- > 2.53.0 >