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From: Thomas Gleixner <tglx@linutronix.de>
To: Shrikanth Hegde <sshegde@linux.ibm.com>,
	LKML <linux-kernel@vger.kernel.org>,
	linuxppc-dev <linuxppc-dev@lists.ozlabs.org>
Cc: Peter Zijlstra <peterz@infradead.org>,
	Gabriele Monaco <gmonaco@redhat.com>,
	Mathieu Desnoyers <mathieu.desnoyers@efficios.com>,
	Michael Jeanson <mjeanson@efficios.com>,
	Jens Axboe <axboe@kernel.dk>,
	"Paul E. McKenney" <paulmck@kernel.org>,
	"Gautham R. Shenoy" <gautham.shenoy@amd.com>,
	Florian Weimer <fweimer@redhat.com>,
	Tim Chen <tim.c.chen@intel.com>,
	Yury Norov <yury.norov@gmail.com>,
	Madhavan Srinivasan <maddy@linux.ibm.com>
Subject: Re: [patch V2 16/20] sched/mmcid: Provide new scheduler CID mechanism
Date: Mon, 27 Oct 2025 09:54:36 +0100	[thread overview]
Message-ID: <87ldkwwwqb.ffs@tglx> (raw)
In-Reply-To: <9076c353-a22b-4c38-bd30-fb10eb0ae851@linux.ibm.com>

On Mon, Oct 27 2025 at 10:41, Shrikanth Hegde wrote:
> On 10/22/25 6:25 PM, Thomas Gleixner wrote:
>> The MM CID management has two fundamental requirements:
>> 
>>    1) It has to guarantee that at no given point in time the same CID is
>>       used by concurrent tasks in userspace.
>> 
>>    2) The CID space must not exceed the number of possible CPUs in a
>>       system. While most allocators (glibc, tcmalloc, jemalloc) do not
>>       care about that, there seems to be at least some LTTng library
>>       depending on it.
>> 
>> The CID space compaction itself is not a functional correctness
>> requirement, it is only a useful optimization mechanism to reduce the
>> memory foot print in unused user space pools.
>> 
>
> Just wondering, if there is no user space request for CID, this whole mechanism
> should be under a static check to avoid any overhead?

The problem is that CID has been introduced unconditionally with RSEQ
and there is no mechanism to opt-in. So we could go and change the ABI,
but as you know that's generally frowned upon.

I thought about adding a static key, but that'd be systemwide and
would probably required to be opt-out for the same reason.

>> +static inline unsigned int mm_get_cid(struct mm_struct *mm)
>> +{
>> +	unsigned int cid = __mm_get_cid(mm, READ_ONCE(mm->mm_cid.max_cids));
>> +
>> +	for (; cid == MM_CID_UNSET; cpu_relax())
>
> This triggers an compile error on ppc64le.
>
> In file included from ./include/vdso/processor.h:10,
>                   from ./arch/powerpc/include/asm/processor.h:9,
>                   from ./include/linux/sched.h:13,
>                   from ./include/linux/sched/affinity.h:1,
>                   from kernel/sched/sched.h:8,
>                   from kernel/sched/rq-offsets.c:5:
> kernel/sched/sched.h: In function ‘mm_get_cid’:
> ./arch/powerpc/include/asm/vdso/processor.h:26:9: error: expected expression before ‘asm’
>     26 |         asm volatile(ASM_FTR_IFCLR(                                     \
>        |         ^~~
> kernel/sched/sched.h:3615:37: note: in expansion of macro ‘cpu_relax’
>   3615 |         for (; cid == MM_CID_UNSET; cpu_relax())
>

Duh. Did not notice because x86 implements cpu_relax() as a static
inline while PPC has it as a plain macro define. Let me move it out of
the for() then.

Thanks,

        tglx



  reply	other threads:[~2025-10-27  8:54 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-22 12:55 [patch V2 00/20] sched: Rewrite MM CID management Thomas Gleixner
2025-10-22 12:55 ` [patch V2 01/20] sched/mmcid: Revert the complex " Thomas Gleixner
2025-10-22 12:55 ` [patch V2 02/20] sched/mmcid: Use proper data structures Thomas Gleixner
2025-10-22 12:55 ` [patch V2 03/20] sched/mmcid: Cacheline align MM CID storage Thomas Gleixner
2025-10-22 12:55 ` [patch V2 04/20] sched: Fixup whitespace damage Thomas Gleixner
2025-10-22 12:55 ` [patch V2 05/20] sched/mmcid: Move scheduler code out of global header Thomas Gleixner
2025-10-22 12:55 ` [patch V2 06/20] sched/mmcid: Prevent pointless work in mm_update_cpus_allowed() Thomas Gleixner
2025-10-22 12:55 ` [patch V2 07/20] cpumask: Introduce cpumask_or_and_calc_weight() Thomas Gleixner
2025-10-23 16:37   ` Yury Norov
2025-10-22 12:55 ` [patch V2 08/20] sched/mmcid: Use cpumask_or_and_calc_weight() Thomas Gleixner
2025-10-23 16:45   ` Yury Norov
2025-10-22 12:55 ` [patch V2 09/20] cpumask: Cache num_possible_cpus() Thomas Gleixner
2025-10-23 16:25   ` Yury Norov
2025-10-22 12:55 ` [patch V2 10/20] sched/mmcid: Convert mm CID mask to a bitmap Thomas Gleixner
2025-10-23 16:46   ` Yury Norov
2025-10-27  5:45   ` Shrikanth Hegde
2025-10-27  8:57     ` Thomas Gleixner
2025-10-22 12:55 ` [patch V2 11/20] signal: Move MMCID exit out of sighand lock Thomas Gleixner
2025-10-22 12:55 ` [patch V2 12/20] sched/mmcid: Move initialization out of line Thomas Gleixner
2025-10-22 12:55 ` [patch V2 13/20] sched/mmcid: Provide precomputed maximal value Thomas Gleixner
2025-10-22 12:55 ` [patch V2 14/20] sched/mmcid: Serialize sched_mm_cid_fork()/exit() with a mutex Thomas Gleixner
2025-10-22 12:55 ` [patch V2 15/20] sched/mmcid: Introduce per task/CPU ownership infrastrcuture Thomas Gleixner
2025-10-22 12:55 ` [patch V2 16/20] sched/mmcid: Provide new scheduler CID mechanism Thomas Gleixner
2025-10-27  5:11   ` Shrikanth Hegde
2025-10-27  8:54     ` Thomas Gleixner [this message]
2025-10-22 12:55 ` [patch V2 17/20] sched/mmcid: Provide CID ownership mode fixup functions Thomas Gleixner
2025-10-22 12:55 ` [patch V2 18/20] irqwork: Move data struct to a types header Thomas Gleixner
2025-10-22 12:55 ` [patch V2 19/20] sched/mmcid: Implement deferred mode change Thomas Gleixner
2025-10-22 12:55 ` [patch V2 20/20] sched/mmcid: Switch over to the new mechanism Thomas Gleixner

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